Re: [PATCH v6 3/4] clk: pistachio: Fix PLL rate calculation in integer mode

[Stephen Boyd <sboyd@codeaurora.org>]

On 08/26, Govindraj Raja wrote:
> From: Zdenko Pulitika <zdenko.pulitika@imgtec.com>
> 
> .recalc_rate callback for the fractional PLL doesn't take operating
> mode into account when calculating PLL rate. This results in
> the incorrect PLL rates when PLL is operating in integer mode.
> 
> Operating mode of fractional PLL is based on the value of the
> fractional divider. Currently it assumes that the PLL will always
> be configured in fractional mode which may not be
> the case. This may result in the wrong output frequency.
> 
> Also vco was calculated based on the current operating mode which
> makes no sense because .set_rate is setting operating mode. Instead,
> vco should be calculated using PLL settings that are about to be set.
> 
> Fixes: 43049b0c83f17("CLK: Pistachio: Add PLL driver")
> Cc: <stable@vger.kernel.org> # 4.1
> Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
> Signed-off-by: Zdenko Pulitika <zdenko.pulitika@imgtec.com>
> Signed-off-by: Govindraj Raja <govindraj.raja@imgtec.com>
> ---

Applied to clk-next

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