From: Andi Kleen <ak@linux.intel.com>
To: Shaohua Li <shli@fb.com>
Cc: Ingo Molnar <mingo@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
x86@kernel.org, linux-kernel@vger.kernel.org, Kernel-team@fb.com,
Suresh Siddha <suresh.b.siddha@intel.com>,
"H. Peter Anvin" <hpa@zytor.com>,
stable@vger.kernel.org, lenb@kernel.org, fenghua.yu@intel.com
Subject: Re: [PATCH] x86: serialize LVTT and TSC_DEADLINE write
Date: Tue, 8 Sep 2015 20:39:37 -0700 [thread overview]
Message-ID: <20150909033937.GH4524@tassilo.jf.intel.com> (raw)
In-Reply-To: <20150805162535.GA2461245@devbig257.prn2.facebook.com>
> Hmm, I didn't mean mfence can't serialize the instructions. For a true
> IO, a serialization can't guarantee device finishes the IO, we generally
> read some safe IO registers to wait IO finish. I completely don't know
> if this case fits here though.
Sorry for the late answer. We (Intel) analyzed this case in detail and
can confirm that the following sequence
1. Memory-mapped write to LVT Timer Register, setting bits 18:17 to 10b.
23. MFENCE.
4. WRMSR to the IA32_TSC_DEADLINE MSR the desired deadline.
has the same effect as the loop algorithm described in the SDM on all Intel
CPUs. So it's fine to use MFENCE here.
-Andi
next prev parent reply other threads:[~2015-09-09 3:39 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-31 22:11 [PATCH] x86: serialize LVTT and TSC_DEADLINE write Shaohua Li
2015-08-01 10:10 ` Thomas Gleixner
2015-08-02 15:49 ` Shaohua Li
2015-08-02 19:41 ` Thomas Gleixner
2015-08-03 23:58 ` Shaohua Li
2015-08-05 8:44 ` Ingo Molnar
2015-08-05 16:25 ` Shaohua Li
2015-09-09 3:39 ` Andi Kleen [this message]
2015-09-09 4:13 ` Shaohua Li
2015-09-09 7:35 ` Thomas Gleixner
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