From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
To: linux-kernel@vger.kernel.org
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
stable@vger.kernel.org, Florian Fainelli <f.fainelli@gmail.com>,
Heiko Stuebner <heiko@sntech.de>,
Dinh Nguyen <dinguyen@opensource.altera.com>,
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
Shawn Guo <shawn.guo@linaro.org>,
Thierry Reding <treding@nvidia.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Michal Simek <michal.simek@xilinx.com>,
Wei Xu <xuwei5@hisilicon.com>,
Russell King <rmk+kernel@arm.linux.org.uk>,
Alexander Kochetkov <al.kochet@gmail.com>
Subject: [PATCH 4.1 34/78] ARM: v7 setup function should invalidate L1 cache
Date: Fri, 11 Sep 2015 15:49:35 -0700 [thread overview]
Message-ID: <20150911224611.228588442@linuxfoundation.org> (raw)
In-Reply-To: <20150911224606.758437370@linuxfoundation.org>
4.1-stable review patch. If anyone has any objections, please let me know.
------------------
From: Russell King <rmk+kernel@arm.linux.org.uk>
commit 02b4e2756e01c623cc4dbceae4b07be75252db5b upstream.
All ARMv5 and older CPUs invalidate their caches in the early assembly
setup function, prior to enabling the MMU. This is because the L1
cache should not contain any data relevant to the execution of the
kernel at this point; all data should have been flushed out to memory.
This requirement should also be true for ARMv6 and ARMv7 CPUs - indeed,
these typically do not search their caches when caching is disabled (as
it needs to be when the MMU is disabled) so this change should be safe.
ARMv7 allows there to be CPUs which search their caches while caching is
disabled, and it's permitted that the cache is uninitialised at boot;
for these, the architecture reference manual requires that an
implementation specific code sequence is used immediately after reset
to ensure that the cache is placed into a sane state. Such
functionality is definitely outside the remit of the Linux kernel, and
must be done by the SoC's firmware before _any_ CPU gets to the Linux
kernel.
Changing the data cache clean+invalidate to a mere invalidate allows us
to get rid of a lot of platform specific hacks around this issue for
their secondary CPU bringup paths - some of which were buggy.
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Tested-by: Florian Fainelli <f.fainelli@gmail.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Wei Xu <xuwei5@hisilicon.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Cc: Alexander Kochetkov <al.kochet@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
arch/arm/mach-bcm/Makefile | 2 +-
arch/arm/mach-bcm/brcmstb.h | 19 -------------------
arch/arm/mach-bcm/headsmp-brcmstb.S | 33 ---------------------------------
arch/arm/mach-bcm/platsmp-brcmstb.c | 4 +---
arch/arm/mach-berlin/headsmp.S | 6 ------
arch/arm/mach-berlin/platsmp.c | 3 +--
arch/arm/mach-hisi/Makefile | 2 +-
arch/arm/mach-hisi/core.h | 1 -
arch/arm/mach-hisi/headsmp.S | 16 ----------------
arch/arm/mach-hisi/platsmp.c | 4 ++--
arch/arm/mach-imx/headsmp.S | 1 -
arch/arm/mach-mvebu/headsmp-a9.S | 1 -
arch/arm/mach-prima2/headsmp.S | 1 -
arch/arm/mach-rockchip/core.h | 1 -
arch/arm/mach-rockchip/headsmp.S | 8 --------
arch/arm/mach-rockchip/platsmp.c | 5 ++---
arch/arm/mach-shmobile/common.h | 1 -
arch/arm/mach-shmobile/headsmp-scu.S | 4 ++--
arch/arm/mach-shmobile/headsmp.S | 7 -------
arch/arm/mach-shmobile/platsmp-apmu.c | 2 +-
arch/arm/mach-socfpga/core.h | 1 -
arch/arm/mach-socfpga/headsmp.S | 5 -----
arch/arm/mach-socfpga/platsmp.c | 2 +-
arch/arm/mach-tegra/Makefile | 2 +-
arch/arm/mach-tegra/headsmp.S | 12 ------------
arch/arm/mach-tegra/reset.c | 2 +-
arch/arm/mach-tegra/reset.h | 1 -
arch/arm/mach-zynq/common.h | 2 --
arch/arm/mach-zynq/headsmp.S | 5 -----
arch/arm/mach-zynq/platsmp.c | 5 ++---
arch/arm/mm/proc-v7.S | 2 +-
31 files changed, 17 insertions(+), 143 deletions(-)
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -43,5 +43,5 @@ obj-$(CONFIG_ARCH_BCM_63XX) := bcm63xx.o
ifeq ($(CONFIG_ARCH_BRCMSTB),y)
CFLAGS_platsmp-brcmstb.o += -march=armv7-a
obj-y += brcmstb.o
-obj-$(CONFIG_SMP) += headsmp-brcmstb.o platsmp-brcmstb.o
+obj-$(CONFIG_SMP) += platsmp-brcmstb.o
endif
--- a/arch/arm/mach-bcm/brcmstb.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * Copyright (C) 2013-2014 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __BRCMSTB_H__
-#define __BRCMSTB_H__
-
-void brcmstb_secondary_startup(void);
-
-#endif /* __BRCMSTB_H__ */
--- a/arch/arm/mach-bcm/headsmp-brcmstb.S
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * SMP boot code for secondary CPUs
- * Based on arch/arm/mach-tegra/headsmp.S
- *
- * Copyright (C) 2010 NVIDIA, Inc.
- * Copyright (C) 2013-2014 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <asm/assembler.h>
-#include <linux/linkage.h>
-#include <linux/init.h>
-
- .section ".text.head", "ax"
-
-ENTRY(brcmstb_secondary_startup)
- /*
- * Ensure CPU is in a sane state by disabling all IRQs and switching
- * into SVC mode.
- */
- setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r0
-
- bl v7_invalidate_l1
- b secondary_startup
-ENDPROC(brcmstb_secondary_startup)
--- a/arch/arm/mach-bcm/platsmp-brcmstb.c
+++ b/arch/arm/mach-bcm/platsmp-brcmstb.c
@@ -30,8 +30,6 @@
#include <asm/mach-types.h>
#include <asm/smp_plat.h>
-#include "brcmstb.h"
-
enum {
ZONE_MAN_CLKEN_MASK = BIT(0),
ZONE_MAN_RESET_CNTL_MASK = BIT(1),
@@ -153,7 +151,7 @@ static void brcmstb_cpu_boot(u32 cpu)
* Set the reset vector to point to the secondary_startup
* routine
*/
- cpu_set_boot_addr(cpu, virt_to_phys(brcmstb_secondary_startup));
+ cpu_set_boot_addr(cpu, virt_to_phys(secondary_startup));
/* Unhalt the cpu */
cpu_rst_cfg_set(cpu, 0);
--- a/arch/arm/mach-berlin/headsmp.S
+++ b/arch/arm/mach-berlin/headsmp.S
@@ -12,12 +12,6 @@
#include <linux/init.h>
#include <asm/assembler.h>
-ENTRY(berlin_secondary_startup)
- ARM_BE8(setend be)
- bl v7_invalidate_l1
- b secondary_startup
-ENDPROC(berlin_secondary_startup)
-
/*
* If the following instruction is set in the reset exception vector, CPUs
* will fetch the value of the software reset address vector when being
--- a/arch/arm/mach-berlin/platsmp.c
+++ b/arch/arm/mach-berlin/platsmp.c
@@ -22,7 +22,6 @@
#define RESET_VECT 0x00
#define SW_RESET_ADDR 0x94
-extern void berlin_secondary_startup(void);
extern u32 boot_inst;
static void __iomem *cpu_ctrl;
@@ -85,7 +84,7 @@ static void __init berlin_smp_prepare_cp
* Write the secondary startup address into the SW reset address
* vector. This is used by boot_inst.
*/
- writel(virt_to_phys(berlin_secondary_startup), vectors_base + SW_RESET_ADDR);
+ writel(virt_to_phys(secondary_startup), vectors_base + SW_RESET_ADDR);
iounmap(vectors_base);
unmap_scu:
--- a/arch/arm/mach-hisi/Makefile
+++ b/arch/arm/mach-hisi/Makefile
@@ -6,4 +6,4 @@ CFLAGS_platmcpm.o := -march=armv7-a
obj-y += hisilicon.o
obj-$(CONFIG_MCPM) += platmcpm.o
-obj-$(CONFIG_SMP) += platsmp.o hotplug.o headsmp.o
+obj-$(CONFIG_SMP) += platsmp.o hotplug.o
--- a/arch/arm/mach-hisi/core.h
+++ b/arch/arm/mach-hisi/core.h
@@ -12,7 +12,6 @@ extern void hi3xxx_cpu_die(unsigned int
extern int hi3xxx_cpu_kill(unsigned int cpu);
extern void hi3xxx_set_cpu(int cpu, bool enable);
-extern void hisi_secondary_startup(void);
extern struct smp_operations hix5hd2_smp_ops;
extern void hix5hd2_set_cpu(int cpu, bool enable);
extern void hix5hd2_cpu_die(unsigned int cpu);
--- a/arch/arm/mach-hisi/headsmp.S
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * Copyright (c) 2014 Hisilicon Limited.
- * Copyright (c) 2014 Linaro Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/linkage.h>
-#include <linux/init.h>
-
- __CPUINIT
-
-ENTRY(hisi_secondary_startup)
- bl v7_invalidate_l1
- b secondary_startup
--- a/arch/arm/mach-hisi/platsmp.c
+++ b/arch/arm/mach-hisi/platsmp.c
@@ -118,7 +118,7 @@ static int hix5hd2_boot_secondary(unsign
{
phys_addr_t jumpaddr;
- jumpaddr = virt_to_phys(hisi_secondary_startup);
+ jumpaddr = virt_to_phys(secondary_startup);
hix5hd2_set_scu_boot_addr(HIX5HD2_BOOT_ADDRESS, jumpaddr);
hix5hd2_set_cpu(cpu, true);
arch_send_wakeup_ipi_mask(cpumask_of(cpu));
@@ -156,7 +156,7 @@ static int hip01_boot_secondary(unsigned
struct device_node *node;
- jumpaddr = virt_to_phys(hisi_secondary_startup);
+ jumpaddr = virt_to_phys(secondary_startup);
hip01_set_boot_addr(HIP01_BOOT_ADDRESS, jumpaddr);
node = of_find_compatible_node(NULL, NULL, "hisilicon,hip01-sysctrl");
--- a/arch/arm/mach-imx/headsmp.S
+++ b/arch/arm/mach-imx/headsmp.S
@@ -25,7 +25,6 @@ diag_reg_offset:
.endm
ENTRY(v7_secondary_startup)
- bl v7_invalidate_l1
set_diag_reg
b secondary_startup
ENDPROC(v7_secondary_startup)
--- a/arch/arm/mach-mvebu/headsmp-a9.S
+++ b/arch/arm/mach-mvebu/headsmp-a9.S
@@ -21,7 +21,6 @@
ENTRY(mvebu_cortex_a9_secondary_startup)
ARM_BE8(setend be)
- bl v7_invalidate_l1
bl armada_38x_scu_power_up
b secondary_startup
ENDPROC(mvebu_cortex_a9_secondary_startup)
--- a/arch/arm/mach-prima2/headsmp.S
+++ b/arch/arm/mach-prima2/headsmp.S
@@ -15,7 +15,6 @@
* ready for them to initialise.
*/
ENTRY(sirfsoc_secondary_startup)
- bl v7_invalidate_l1
mrc p15, 0, r0, c0, c0, 5
and r0, r0, #15
adr r4, 1f
--- a/arch/arm/mach-rockchip/core.h
+++ b/arch/arm/mach-rockchip/core.h
@@ -17,4 +17,3 @@ extern char rockchip_secondary_trampolin
extern char rockchip_secondary_trampoline_end;
extern unsigned long rockchip_boot_fn;
-extern void rockchip_secondary_startup(void);
--- a/arch/arm/mach-rockchip/headsmp.S
+++ b/arch/arm/mach-rockchip/headsmp.S
@@ -15,14 +15,6 @@
#include <linux/linkage.h>
#include <linux/init.h>
-ENTRY(rockchip_secondary_startup)
- mrc p15, 0, r0, c0, c0, 0 @ read main ID register
- ldr r1, =0x00000c09 @ Cortex-A9 primary part number
- teq r0, r1
- beq v7_invalidate_l1
- b secondary_startup
-ENDPROC(rockchip_secondary_startup)
-
ENTRY(rockchip_secondary_trampoline)
ldr pc, 1f
ENDPROC(rockchip_secondary_trampoline)
--- a/arch/arm/mach-rockchip/platsmp.c
+++ b/arch/arm/mach-rockchip/platsmp.c
@@ -149,8 +149,7 @@ static int __cpuinit rockchip_boot_secon
* sram_base_addr + 8: start address for pc
* */
udelay(10);
- writel(virt_to_phys(rockchip_secondary_startup),
- sram_base_addr + 8);
+ writel(virt_to_phys(secondary_startup), sram_base_addr + 8);
writel(0xDEADBEAF, sram_base_addr + 4);
dsb_sev();
}
@@ -189,7 +188,7 @@ static int __init rockchip_smp_prepare_s
}
/* set the boot function for the sram code */
- rockchip_boot_fn = virt_to_phys(rockchip_secondary_startup);
+ rockchip_boot_fn = virt_to_phys(secondary_startup);
/* copy the trampoline to sram, that runs during startup of the core */
memcpy(sram_base_addr, &rockchip_secondary_trampoline, trampoline_sz);
--- a/arch/arm/mach-shmobile/common.h
+++ b/arch/arm/mach-shmobile/common.h
@@ -14,7 +14,6 @@ extern void shmobile_smp_sleep(void);
extern void shmobile_smp_hook(unsigned int cpu, unsigned long fn,
unsigned long arg);
extern int shmobile_smp_cpu_disable(unsigned int cpu);
-extern void shmobile_invalidate_start(void);
extern void shmobile_boot_scu(void);
extern void shmobile_smp_scu_prepare_cpus(unsigned int max_cpus);
extern void shmobile_smp_scu_cpu_die(unsigned int cpu);
--- a/arch/arm/mach-shmobile/headsmp-scu.S
+++ b/arch/arm/mach-shmobile/headsmp-scu.S
@@ -22,7 +22,7 @@
* Boot code for secondary CPUs.
*
* First we turn on L1 cache coherency for our CPU. Then we jump to
- * shmobile_invalidate_start that invalidates the cache and hands over control
+ * secondary_startup that invalidates the cache and hands over control
* to the common ARM startup code.
*/
ENTRY(shmobile_boot_scu)
@@ -36,7 +36,7 @@ ENTRY(shmobile_boot_scu)
bic r2, r2, r3 @ Clear bits of our CPU (Run Mode)
str r2, [r0, #8] @ write back
- b shmobile_invalidate_start
+ b secondary_startup
ENDPROC(shmobile_boot_scu)
.text
--- a/arch/arm/mach-shmobile/headsmp.S
+++ b/arch/arm/mach-shmobile/headsmp.S
@@ -16,13 +16,6 @@
#include <asm/assembler.h>
#include <asm/memory.h>
-#ifdef CONFIG_SMP
-ENTRY(shmobile_invalidate_start)
- bl v7_invalidate_l1
- b secondary_startup
-ENDPROC(shmobile_invalidate_start)
-#endif
-
/*
* Reset vector for secondary CPUs.
* This will be mapped at address 0 by SBAR register.
--- a/arch/arm/mach-shmobile/platsmp-apmu.c
+++ b/arch/arm/mach-shmobile/platsmp-apmu.c
@@ -133,7 +133,7 @@ void __init shmobile_smp_apmu_prepare_cp
int shmobile_smp_apmu_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
/* For this particular CPU register boot vector */
- shmobile_smp_hook(cpu, virt_to_phys(shmobile_invalidate_start), 0);
+ shmobile_smp_hook(cpu, virt_to_phys(secondary_startup), 0);
return apmu_wrap(cpu, apmu_power_on);
}
--- a/arch/arm/mach-socfpga/core.h
+++ b/arch/arm/mach-socfpga/core.h
@@ -31,7 +31,6 @@
#define RSTMGR_MPUMODRST_CPU1 0x2 /* CPU1 Reset */
-extern void socfpga_secondary_startup(void);
extern void __iomem *socfpga_scu_base_addr;
extern void socfpga_init_clocks(void);
--- a/arch/arm/mach-socfpga/headsmp.S
+++ b/arch/arm/mach-socfpga/headsmp.S
@@ -30,8 +30,3 @@ ENTRY(secondary_trampoline)
1: .long .
.long socfpga_cpu1start_addr
ENTRY(secondary_trampoline_end)
-
-ENTRY(socfpga_secondary_startup)
- bl v7_invalidate_l1
- b secondary_startup
-ENDPROC(socfpga_secondary_startup)
--- a/arch/arm/mach-socfpga/platsmp.c
+++ b/arch/arm/mach-socfpga/platsmp.c
@@ -40,7 +40,7 @@ static int socfpga_boot_secondary(unsign
memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
- writel(virt_to_phys(socfpga_secondary_startup),
+ writel(virt_to_phys(secondary_startup),
sys_manager_base_addr + (socfpga_cpu1start_addr & 0x000000ff));
flush_cache_all();
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -19,7 +19,7 @@ obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pm-t
ifeq ($(CONFIG_CPU_IDLE),y)
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += cpuidle-tegra30.o
endif
-obj-$(CONFIG_SMP) += platsmp.o headsmp.o
+obj-$(CONFIG_SMP) += platsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
obj-$(CONFIG_ARCH_TEGRA_114_SOC) += sleep-tegra30.o
--- a/arch/arm/mach-tegra/headsmp.S
+++ /dev/null
@@ -1,12 +0,0 @@
-#include <linux/linkage.h>
-#include <linux/init.h>
-
-#include "sleep.h"
-
- .section ".text.head", "ax"
-
-ENTRY(tegra_secondary_startup)
- check_cpu_part_num 0xc09, r8, r9
- bleq v7_invalidate_l1
- b secondary_startup
-ENDPROC(tegra_secondary_startup)
--- a/arch/arm/mach-tegra/reset.c
+++ b/arch/arm/mach-tegra/reset.c
@@ -94,7 +94,7 @@ void __init tegra_cpu_reset_handler_init
__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] =
*((u32 *)cpu_possible_mask);
__tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_SECONDARY] =
- virt_to_phys((void *)tegra_secondary_startup);
+ virt_to_phys((void *)secondary_startup);
#endif
#ifdef CONFIG_PM_SLEEP
--- a/arch/arm/mach-tegra/reset.h
+++ b/arch/arm/mach-tegra/reset.h
@@ -37,7 +37,6 @@ void __tegra_cpu_reset_handler_start(voi
void __tegra_cpu_reset_handler(void);
void __tegra20_cpu1_resettable_status_offset(void);
void __tegra_cpu_reset_handler_end(void);
-void tegra_secondary_startup(void);
#ifdef CONFIG_PM_SLEEP
#define tegra_cpu_lp1_mask \
--- a/arch/arm/mach-zynq/common.h
+++ b/arch/arm/mach-zynq/common.h
@@ -17,8 +17,6 @@
#ifndef __MACH_ZYNQ_COMMON_H__
#define __MACH_ZYNQ_COMMON_H__
-void zynq_secondary_startup(void);
-
extern int zynq_slcr_init(void);
extern int zynq_early_slcr_init(void);
extern void zynq_slcr_system_reset(void);
--- a/arch/arm/mach-zynq/headsmp.S
+++ b/arch/arm/mach-zynq/headsmp.S
@@ -22,8 +22,3 @@ zynq_secondary_trampoline_jump:
.globl zynq_secondary_trampoline_end
zynq_secondary_trampoline_end:
ENDPROC(zynq_secondary_trampoline)
-
-ENTRY(zynq_secondary_startup)
- bl v7_invalidate_l1
- b secondary_startup
-ENDPROC(zynq_secondary_startup)
--- a/arch/arm/mach-zynq/platsmp.c
+++ b/arch/arm/mach-zynq/platsmp.c
@@ -87,10 +87,9 @@ int zynq_cpun_start(u32 address, int cpu
}
EXPORT_SYMBOL(zynq_cpun_start);
-static int zynq_boot_secondary(unsigned int cpu,
- struct task_struct *idle)
+static int zynq_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
- return zynq_cpun_start(virt_to_phys(zynq_secondary_startup), cpu);
+ return zynq_cpun_start(virt_to_phys(secondary_startup), cpu);
}
/*
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -336,7 +336,7 @@ __v7_pj4b_setup:
__v7_setup:
adr r12, __v7_setup_stack @ the local stack
stmia r12, {r0-r5, r7, r9, r11, lr}
- bl v7_flush_dcache_louis
+ bl v7_invalidate_l1
ldmia r12, {r0-r5, r7, r9, r11, lr}
mrc p15, 0, r0, c0, c0, 0 @ read main ID register
next prev parent reply other threads:[~2015-09-11 22:50 UTC|newest]
Thread overview: 86+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-11 22:49 [PATCH 4.1 00/78] 4.1.6-stable review Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 01/78] ipc,sem: fix use after free on IPC_RMID after a task using same semaphore set exits Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 02/78] ipc/sem.c: update/correct memory barriers Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 03/78] mm/hwpoison: fix page refcount of unknown non LRU page Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 04/78] mm/hwpoison: fix fail isolate hugetlbfs page w/ refcount held Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 05/78] clk: pxa: pxa3xx: fix CKEN register access Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 08/78] rsi: Fix failure to load firmware after memory leak fix and fix the leak Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 09/78] perf: Fix fasync handling on inherited events Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 10/78] perf: Fix running time accounting Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 11/78] perf: Fix double-free of the AUX buffer Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 12/78] perf: Fix PERF_EVENT_IOC_PERIOD migration race Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 13/78] iwlwifi: pcie: fix prepare card flow Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 14/78] rtlwifi: rtl8723be: Add module parameter for MSI interrupts Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 15/78] rtlwifi: Fix NULL dereference when PCI driver used as an AP Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 16/78] x86/xen: build "Xen PV" APIC driver for domU as well Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 17/78] xen/xenbus: Dont leak memory when unmapping the ring on HVM backend Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 18/78] dm thin metadata: delete btrees when releasing metadata snapshot Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 19/78] localmodconfig: Use Kbuild files too Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 20/78] EDAC, ppc4xx: Access mci->csrows array elements properly Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 21/78] HID: hid-input: Fix accessing freed memory during device disconnect Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 22/78] HID: uclogic: fix limit in uclogic_tablet_enable() Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 23/78] drm/radeon: add new OLAND pci id Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 24/78] drm/vmwgfx: Fix execbuf locking issues Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 25/78] libfc: Fix fc_exch_recv_req() error path Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 26/78] libfc: Fix fc_fcp_cleanup_each_cmd() Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 27/78] ARM: imx6: correct i.MX6 PCIe interrupt routing Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 28/78] ARM: dts: omap243x: Fix broken pbias device creation Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 29/78] ARM: dts: dra7: " Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 30/78] ARM: dts: OMAP4: " Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 31/78] ARM: dts: OMAP5: " Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 32/78] ARM: 8385/1: VDSO: group link options Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 33/78] ARM: 8384/1: VDSO: force use of BFD linker Greg Kroah-Hartman
2015-09-11 22:49 ` Greg Kroah-Hartman [this message]
2015-09-11 22:49 ` [PATCH 4.1 35/78] ARM: invalidate L1 before enabling coherency Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 36/78] mfd: arizona: Fix initialisation of the PM runtime Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 37/78] Revert x86 sigcontext cleanups Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 38/78] regmap: regcache-rbtree: Clean new present bits on present bitmap resize Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 39/78] MIPS: Fix seccomp syscall argument for MIPS64 Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 40/78] libiscsi: Fix host busy blocking during connection teardown Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 41/78] sd: Fix maximum I/O size for BLOCK_PC requests Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 42/78] crypto: nx - respect sg limit bounds when building sg lists for SHA Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 43/78] crypto: caam - fix memory corruption in ahash_final_ctx Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 44/78] Revert "libata-eh: Set information field for autosense" Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 45/78] Revert "libata: Implement support for sense data reporting" Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 46/78] Revert "libata: Implement NCQ autosense" Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 48/78] ALSA: usb-audio: Fix runtime PM unbalance Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 49/78] ALSA: hda - Fix the white noise on Dell laptop Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 50/78] ALSA: usb: Add native DSD support for Gustard DAC-X20U Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 51/78] ALSA: hda - Shutdown CX20722 on reboot/free to avoid spurious noises Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 52/78] ALSA: hda - Check all inputs for is_active_nid_for_any() Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 53/78] ALSA: hda - Fix path power activation Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 54/78] ALSA: hda: fix possible NULL dereference Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 55/78] mac80211: fix invalid read in minstrel_sort_best_tp_rates() Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 56/78] target/iscsi: Fix double free of a TUR followed by a solicited NOPOUT Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 57/78] PCI: Dont use 64-bit bus addresses on PA-RISC Greg Kroah-Hartman
2015-09-11 22:49 ` [PATCH 4.1 58/78] Input: gpio_keys_polled - request GPIO pin as input Greg Kroah-Hartman
2015-09-11 22:50 ` [PATCH 4.1 59/78] drm/atmel-hlcdc: Compile suspend/resume for PM_SLEEP only Greg Kroah-Hartman
2015-09-11 22:50 ` [PATCH 4.1 60/78] drm/i915: Flag the execlists context object as dirty after every use Greg Kroah-Hartman
2015-09-11 22:50 ` [PATCH 4.1 63/78] 9p: ensure err is initialized to 0 in p9_client_read/write Greg Kroah-Hartman
2015-09-11 22:50 ` [PATCH 4.1 64/78] irqchip/crossbar: Restore the irq_set_type() mechanism Greg Kroah-Hartman
2015-09-11 22:50 ` [PATCH 4.1 65/78] irqchip/crossbar: Restore the mask on suspend behaviour Greg Kroah-Hartman
2015-09-11 22:50 ` [PATCH 4.1 66/78] irqchip/crossbar: Restore set_wake functionality Greg Kroah-Hartman
2015-09-11 22:50 ` [PATCH 4.1 67/78] ARM: OMAP: wakeupgen: Restore the irq_set_type() mechanism Greg Kroah-Hartman
2015-09-11 22:50 ` [PATCH 4.1 68/78] genirq: Dont return ENOSYS in irq_chip_retrigger_hierarchy Greg Kroah-Hartman
2015-09-11 22:50 ` [PATCH 4.1 69/78] genirq: Introduce irq_chip_set_type_parent() helper Greg Kroah-Hartman
2015-09-11 22:50 ` [PATCH 4.1 71/78] can: pcan_usb: dont provide CAN FD bittimings by non-FD adapters Greg Kroah-Hartman
2015-09-11 22:50 ` [PATCH 4.1 72/78] Add factory recertified Crucial M500s to blacklist Greg Kroah-Hartman
2015-09-11 22:50 ` [PATCH 4.1 73/78] fnic: Use the local variable instead of I/O flag to acquire io_req_lock in fnic_queuecommand() to avoid deadloack Greg Kroah-Hartman
2015-09-11 22:50 ` [PATCH 4.1 74/78] arm64: KVM: Fix host crash when injecting a fault into a 32bit guest Greg Kroah-Hartman
2015-09-11 22:50 ` [PATCH 4.1 75/78] arm64: perf: fix unassigned cpu_pmu->plat_device when probing PMU PPIs Greg Kroah-Hartman
2015-09-11 22:50 ` [PATCH 4.1 76/78] x86/xen: make CONFIG_XEN depend on CONFIG_X86_LOCAL_APIC Greg Kroah-Hartman
2015-09-11 22:50 ` [PATCH 4.1 77/78] x86/apic: Fix fallout from x2apic cleanup Greg Kroah-Hartman
2015-09-11 22:50 ` [PATCH 4.1 78/78] x86/idle: Restore trace_cpu_idle to mwait_idle() calls Greg Kroah-Hartman
2015-09-11 23:15 ` [PATCH 4.1 00/78] 4.1.6-stable review Christoph Biedl
2015-09-12 0:59 ` Greg KH
2015-09-11 23:16 ` Holger Hoffstätte
2015-09-12 0:59 ` Greg KH
2015-09-12 0:16 ` Shuah Khan
2015-09-12 1:00 ` Greg Kroah-Hartman
2015-09-12 1:00 ` [PATCH 4.1 00/78] 4.1.7-stable review Greg Kroah-Hartman
2015-09-12 2:10 ` Shuah Khan
2015-09-12 4:39 ` Greg Kroah-Hartman
2015-09-12 4:25 ` Guenter Roeck
2015-09-12 4:39 ` Greg Kroah-Hartman
2015-09-12 8:53 ` Sudip Mukherjee
2015-09-12 15:55 ` Greg Kroah-Hartman
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