* [PATCH 0/3] Patches to apply to v4.1-stable
@ 2015-08-15 0:32 Alexander Kochetkov
2015-08-15 0:32 ` [PATCH 1/3] ARM: 8385/1: VDSO: group link options Alexander Kochetkov
` (3 more replies)
0 siblings, 4 replies; 11+ messages in thread
From: Alexander Kochetkov @ 2015-08-15 0:32 UTC (permalink / raw)
To: stable; +Cc: Alexander Kochetkov
Hi Greg,
Please apply the following three patches to v4.1-stable.
They fixes regressions introduced somethere between 3.18.20 and 4.1.5.
The first two patches fixes kernel build failure caused by
Linaro toolchain (GCC 4.9-2015.03) 4.9.3 20150311:
BFD: arch/arm/vdso/vdso.so: Not enough room for program headers, try linking with -N
arm-angstrom-linux-gnueabi-objcopy:arch/arm/vdso/vdso.so[.hash]: Bad value
The third patch fixes regression introduced in rk3188 board by commit
'3ee851e212d0bb6be8c462059fba74ce2e3f6064 ARM: rockchip: add basic smp
support for rk3288'. Regression cause kernel hang on line 'Starting kernel ...'.
Hangs happens randomly after poweron and always after reboot.
Another problem caused by regression is random koops, like one shown below.
Actually, I don't understand how guys managed to run rk3288 with the
3ee851e commit. Here (https://patchwork.ozlabs.org/patch/474075/)
Russell King describe problems that 3ee851e has.
Instead of reverting 3ee851e212d0bb6be8c4620, I'd suggest to backport
upstream patch (02b4e2756e01c623cc4dbceae4b07be75252db5b), that do the same.
Thanks,
Alexander.
BUG: Bad page state in process memsize pfn:95ca7
page:ef6b34e0 count:1638778872 mapcount:0 mapping:9cfe0f3b index:0x2
flags: 0xa4734918(uptodate|dirty|owner_priv_1|private|head|swapcache|mappedtodisk|unevictable|mlocked)
page dumped because: PAGE_FLAGS_CHECK_AT_PREP flag set
bad because of flags:
flags: 0x334918(uptodate|dirty|owner_priv_1|private|head|swapcache|mappedtodisk|unevictable|mlocked)
Modules linked in:
CPU: 2 PID: 316 Comm: memsize Not tainted 4.1.4 #3
Hardware name: Rockchip (Device Tree)
[<c0015f08>] (unwind_backtrace) from [<c0012318>] (show_stack+0x10/0x14)
[<c0012318>] (show_stack) from [<c0442fb8>] (dump_stack+0x70/0x8c)
[<c0442fb8>] (dump_stack) from [<c009ad8c>] (bad_page+0xe0/0x110)
[<c009ad8c>] (bad_page) from [<c009d6fc>] (get_page_from_freelist+0x420/0x56c)
[<c009d6fc>] (get_page_from_freelist) from [<c009d97c>] (__alloc_pages_nodemask+0x134/0x6d0)
[<c009d97c>] (__alloc_pages_nodemask) from [<c00b4cbc>] (handle_mm_fault+0x78c/0xcf4)
[<c00b4cbc>] (handle_mm_fault) from [<c001d308>] (do_page_fault+0x128/0x30c)
[<c001d308>] (do_page_fault) from [<c0009214>] (do_DataAbort+0x34/0xb4)
[<c0009214>] (do_DataAbort) from [<c0012fdc>] (__dabt_usr+0x3c/0x40)
Exception stack(0xee36ffb0 to 0xee36fff8)
ffa0: a62e4008 00b61000 00001000 00000000
ffc0: 00001000 0000d204 00000fff 00000000 00020000 00c80000 00000064 0000d204
ffe0: 0000d164 beed6b88 00008fa5 00008d94 600c0030 ffffffff
Disabling lock debugging due to kernel taint
Nathan Lynch (2):
ARM: 8385/1: VDSO: group link options
ARM: 8384/1: VDSO: force use of BFD linker
Russell King (1):
ARM: v7 setup function should invalidate L1 cache
arch/arm/mach-bcm/Makefile | 2 +-
arch/arm/mach-bcm/brcmstb.h | 19 -------------------
arch/arm/mach-bcm/headsmp-brcmstb.S | 33 ---------------------------------
arch/arm/mach-bcm/platsmp-brcmstb.c | 4 +---
arch/arm/mach-berlin/headsmp.S | 6 ------
arch/arm/mach-berlin/platsmp.c | 3 +--
arch/arm/mach-hisi/Makefile | 2 +-
arch/arm/mach-hisi/core.h | 1 -
arch/arm/mach-hisi/headsmp.S | 16 ----------------
arch/arm/mach-hisi/platsmp.c | 4 ++--
arch/arm/mach-imx/headsmp.S | 1 -
arch/arm/mach-mvebu/headsmp-a9.S | 1 -
arch/arm/mach-prima2/headsmp.S | 1 -
arch/arm/mach-rockchip/core.h | 1 -
arch/arm/mach-rockchip/headsmp.S | 8 --------
arch/arm/mach-rockchip/platsmp.c | 5 ++---
arch/arm/mach-shmobile/common.h | 1 -
arch/arm/mach-shmobile/headsmp-scu.S | 4 ++--
arch/arm/mach-shmobile/headsmp.S | 7 -------
arch/arm/mach-shmobile/platsmp-apmu.c | 2 +-
arch/arm/mach-socfpga/core.h | 1 -
arch/arm/mach-socfpga/headsmp.S | 5 -----
arch/arm/mach-socfpga/platsmp.c | 2 +-
arch/arm/mach-tegra/Makefile | 2 +-
arch/arm/mach-tegra/headsmp.S | 12 ------------
arch/arm/mach-tegra/reset.c | 2 +-
arch/arm/mach-tegra/reset.h | 1 -
arch/arm/mach-zynq/common.h | 2 --
arch/arm/mach-zynq/headsmp.S | 5 -----
arch/arm/mach-zynq/platsmp.c | 5 ++---
arch/arm/mm/proc-v7.S | 2 +-
arch/arm/vdso/Makefile | 18 +++++++++++-------
32 files changed, 28 insertions(+), 150 deletions(-)
delete mode 100644 arch/arm/mach-bcm/brcmstb.h
delete mode 100644 arch/arm/mach-bcm/headsmp-brcmstb.S
delete mode 100644 arch/arm/mach-hisi/headsmp.S
delete mode 100644 arch/arm/mach-tegra/headsmp.S
--
1.7.9.5
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 1/3] ARM: 8385/1: VDSO: group link options
2015-08-15 0:32 [PATCH 0/3] Patches to apply to v4.1-stable Alexander Kochetkov
@ 2015-08-15 0:32 ` Alexander Kochetkov
2015-08-19 21:05 ` Nathan Lynch
2015-08-15 0:32 ` [PATCH 2/3] ARM: 8384/1: VDSO: force use of BFD linker Alexander Kochetkov
` (2 subsequent siblings)
3 siblings, 1 reply; 11+ messages in thread
From: Alexander Kochetkov @ 2015-08-15 0:32 UTC (permalink / raw)
To: stable; +Cc: Nathan Lynch, Russell King
From: Nathan Lynch <nathan_lynch@mentor.com>
commit d33ce23b2160d26b27a47092da5d556b5b11a12a upstream.
Currently the VDSO's link options are kind of a mess spread between
ccflags-y and cmd_vdsold. Collect linker directives into one
variable, VDSO_LDFLAGS, and use that in cmd_vdsold.
Signed-off-by: Nathan Lynch <nathan_lynch@mentor.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
arch/arm/vdso/Makefile | 17 ++++++++++-------
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/arch/arm/vdso/Makefile b/arch/arm/vdso/Makefile
index 8aa79105..89182ad 100644
--- a/arch/arm/vdso/Makefile
+++ b/arch/arm/vdso/Makefile
@@ -6,9 +6,14 @@ obj-vdso := vgettimeofday.o datapage.o
targets := $(obj-vdso) vdso.so vdso.so.dbg vdso.so.raw vdso.lds
obj-vdso := $(addprefix $(obj)/, $(obj-vdso))
-ccflags-y := -shared -fPIC -fno-common -fno-builtin -fno-stack-protector
-ccflags-y += -nostdlib -Wl,-soname=linux-vdso.so.1 -DDISABLE_BRANCH_PROFILING
-ccflags-y += -Wl,--no-undefined $(call cc-ldoption, -Wl$(comma)--hash-style=sysv)
+ccflags-y := -fPIC -fno-common -fno-builtin -fno-stack-protector
+ccflags-y += -DDISABLE_BRANCH_PROFILING
+
+VDSO_LDFLAGS := -Wl,-Bsymbolic -Wl,--no-undefined -Wl,-soname=linux-vdso.so.1
+VDSO_LDFLAGS += -Wl,-z,max-page-size=4096 -Wl,-z,common-page-size=4096
+VDSO_LDFLAGS += -nostdlib -shared
+VDSO_LDFLAGS += $(call cc-ldoption, -Wl$(comma)--hash-style=sysv)
+VDSO_LDFLAGS += $(call cc-ldoption, -Wl$(comma)--build-id)
obj-$(CONFIG_VDSO) += vdso.o
extra-$(CONFIG_VDSO) += vdso.lds
@@ -40,10 +45,8 @@ $(obj)/%.so: $(obj)/%.so.dbg FORCE
# Actual build commands
quiet_cmd_vdsold = VDSO $@
- cmd_vdsold = $(CC) $(c_flags) -Wl,-T $(filter %.lds,$^) $(filter %.o,$^) \
- $(call cc-ldoption, -Wl$(comma)--build-id) \
- -Wl,-Bsymbolic -Wl,-z,max-page-size=4096 \
- -Wl,-z,common-page-size=4096 -o $@
+ cmd_vdsold = $(CC) $(c_flags) $(VDSO_LDFLAGS) \
+ -Wl,-T $(filter %.lds,$^) $(filter %.o,$^) -o $@
quiet_cmd_vdsomunge = MUNGE $@
cmd_vdsomunge = $(objtree)/$(obj)/vdsomunge $< $@
--
1.7.9.5
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 2/3] ARM: 8384/1: VDSO: force use of BFD linker
2015-08-15 0:32 [PATCH 0/3] Patches to apply to v4.1-stable Alexander Kochetkov
2015-08-15 0:32 ` [PATCH 1/3] ARM: 8385/1: VDSO: group link options Alexander Kochetkov
@ 2015-08-15 0:32 ` Alexander Kochetkov
2015-08-15 0:32 ` [PATCH 3/3] ARM: v7 setup function should invalidate L1 cache Alexander Kochetkov
2015-09-11 6:11 ` [PATCH 0/3] Patches to apply to v4.1-stable Greg KH
3 siblings, 0 replies; 11+ messages in thread
From: Alexander Kochetkov @ 2015-08-15 0:32 UTC (permalink / raw)
To: stable; +Cc: Nathan Lynch, Russell King
From: Nathan Lynch <nathan_lynch@mentor.com>
commit d2b30cd4b7223a96e606dfc8120626f66d81e091 upstream.
When using a toolchain with gold as the default linker, the VDSO build
fails:
VDSO arch/arm/vdso/vdso.so.raw
HOSTCC arch/arm/vdso/vdsomunge
MUNGE arch/arm/vdso/vdso.so.dbg
OBJCOPY arch/arm/vdso/vdso.so
BFD: arch/arm/vdso/vdso.so: Not enough room for program headers, try
linking with -N
For whatever reason, ld.gold is omitting an exidx program header that
ld.bfd emits, and even when I work around that, I don't get a working
VDSO.
For now, instead of supporting gold (which will fail to link the
kernel anyway since it does not implement --pic-veneer), direct the
compiler to use the traditional bfd linker. This is accomplished by
using -fuse-ld, which is implemented in GCC 4.8 and later.
Note: one limitation of this is that if the toolchain is configured
to use gold by default, and the bfd linker is not in $PATH, the VDSO
build will fail:
VDSO arch/arm/vdso/vdso.so.raw
collect2: fatal error: cannot find 'ld'
This will happen if CROSS_COMPILE begins with a path such as
/opt/bin/arm-linux-gnu- but /opt/bin is not in $PATH. This is
considered an acceptable corner-case limitation and is easily worked
around.
Additonal note: we use cc-option instead of cc-ldoption so that
-fuse-ld=bfd is placed in the command line if the compiler recognizes
the option. Using cc-ldoption results in an attempt to link, which
fails in the situation just described, causing -fuse-ld=bfd to be
omitted and gold to be used for the VDSO link, which is what we're
trying to prevent.
Reported-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Nathan Lynch <nathan_lynch@mentor.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
arch/arm/vdso/Makefile | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/vdso/Makefile b/arch/arm/vdso/Makefile
index 89182ad..9d259d9 100644
--- a/arch/arm/vdso/Makefile
+++ b/arch/arm/vdso/Makefile
@@ -14,6 +14,7 @@ VDSO_LDFLAGS += -Wl,-z,max-page-size=4096 -Wl,-z,common-page-size=4096
VDSO_LDFLAGS += -nostdlib -shared
VDSO_LDFLAGS += $(call cc-ldoption, -Wl$(comma)--hash-style=sysv)
VDSO_LDFLAGS += $(call cc-ldoption, -Wl$(comma)--build-id)
+VDSO_LDFLAGS += $(call cc-option, -fuse-ld=bfd)
obj-$(CONFIG_VDSO) += vdso.o
extra-$(CONFIG_VDSO) += vdso.lds
--
1.7.9.5
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 3/3] ARM: v7 setup function should invalidate L1 cache
2015-08-15 0:32 [PATCH 0/3] Patches to apply to v4.1-stable Alexander Kochetkov
2015-08-15 0:32 ` [PATCH 1/3] ARM: 8385/1: VDSO: group link options Alexander Kochetkov
2015-08-15 0:32 ` [PATCH 2/3] ARM: 8384/1: VDSO: force use of BFD linker Alexander Kochetkov
@ 2015-08-15 0:32 ` Alexander Kochetkov
2015-08-15 8:00 ` Russell King - ARM Linux
2015-09-11 6:11 ` [PATCH 0/3] Patches to apply to v4.1-stable Greg KH
3 siblings, 1 reply; 11+ messages in thread
From: Alexander Kochetkov @ 2015-08-15 0:32 UTC (permalink / raw)
To: stable; +Cc: Russell King
From: Russell King <rmk+kernel@arm.linux.org.uk>
commit 02b4e2756e01c623cc4dbceae4b07be75252db5b upstream.
All ARMv5 and older CPUs invalidate their caches in the early assembly
setup function, prior to enabling the MMU. This is because the L1
cache should not contain any data relevant to the execution of the
kernel at this point; all data should have been flushed out to memory.
This requirement should also be true for ARMv6 and ARMv7 CPUs - indeed,
these typically do not search their caches when caching is disabled (as
it needs to be when the MMU is disabled) so this change should be safe.
ARMv7 allows there to be CPUs which search their caches while caching is
disabled, and it's permitted that the cache is uninitialised at boot;
for these, the architecture reference manual requires that an
implementation specific code sequence is used immediately after reset
to ensure that the cache is placed into a sane state. Such
functionality is definitely outside the remit of the Linux kernel, and
must be done by the SoC's firmware before _any_ CPU gets to the Linux
kernel.
Changing the data cache clean+invalidate to a mere invalidate allows us
to get rid of a lot of platform specific hacks around this issue for
their secondary CPU bringup paths - some of which were buggy.
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Tested-by: Florian Fainelli <f.fainelli@gmail.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Wei Xu <xuwei5@hisilicon.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
arch/arm/mach-bcm/Makefile | 2 +-
arch/arm/mach-bcm/brcmstb.h | 19 -------------------
arch/arm/mach-bcm/headsmp-brcmstb.S | 33 ---------------------------------
arch/arm/mach-bcm/platsmp-brcmstb.c | 4 +---
arch/arm/mach-berlin/headsmp.S | 6 ------
arch/arm/mach-berlin/platsmp.c | 3 +--
arch/arm/mach-hisi/Makefile | 2 +-
arch/arm/mach-hisi/core.h | 1 -
arch/arm/mach-hisi/headsmp.S | 16 ----------------
arch/arm/mach-hisi/platsmp.c | 4 ++--
arch/arm/mach-imx/headsmp.S | 1 -
arch/arm/mach-mvebu/headsmp-a9.S | 1 -
arch/arm/mach-prima2/headsmp.S | 1 -
arch/arm/mach-rockchip/core.h | 1 -
arch/arm/mach-rockchip/headsmp.S | 8 --------
arch/arm/mach-rockchip/platsmp.c | 5 ++---
arch/arm/mach-shmobile/common.h | 1 -
arch/arm/mach-shmobile/headsmp-scu.S | 4 ++--
arch/arm/mach-shmobile/headsmp.S | 7 -------
arch/arm/mach-shmobile/platsmp-apmu.c | 2 +-
arch/arm/mach-socfpga/core.h | 1 -
arch/arm/mach-socfpga/headsmp.S | 5 -----
arch/arm/mach-socfpga/platsmp.c | 2 +-
arch/arm/mach-tegra/Makefile | 2 +-
arch/arm/mach-tegra/headsmp.S | 12 ------------
arch/arm/mach-tegra/reset.c | 2 +-
arch/arm/mach-tegra/reset.h | 1 -
arch/arm/mach-zynq/common.h | 2 --
arch/arm/mach-zynq/headsmp.S | 5 -----
arch/arm/mach-zynq/platsmp.c | 5 ++---
arch/arm/mm/proc-v7.S | 2 +-
31 files changed, 17 insertions(+), 143 deletions(-)
delete mode 100644 arch/arm/mach-bcm/brcmstb.h
delete mode 100644 arch/arm/mach-bcm/headsmp-brcmstb.S
delete mode 100644 arch/arm/mach-hisi/headsmp.S
delete mode 100644 arch/arm/mach-tegra/headsmp.S
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index 4c38674..54d274d 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -43,5 +43,5 @@ obj-$(CONFIG_ARCH_BCM_63XX) := bcm63xx.o
ifeq ($(CONFIG_ARCH_BRCMSTB),y)
CFLAGS_platsmp-brcmstb.o += -march=armv7-a
obj-y += brcmstb.o
-obj-$(CONFIG_SMP) += headsmp-brcmstb.o platsmp-brcmstb.o
+obj-$(CONFIG_SMP) += platsmp-brcmstb.o
endif
diff --git a/arch/arm/mach-bcm/brcmstb.h b/arch/arm/mach-bcm/brcmstb.h
deleted file mode 100644
index ec0c3d1..0000000
--- a/arch/arm/mach-bcm/brcmstb.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * Copyright (C) 2013-2014 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __BRCMSTB_H__
-#define __BRCMSTB_H__
-
-void brcmstb_secondary_startup(void);
-
-#endif /* __BRCMSTB_H__ */
diff --git a/arch/arm/mach-bcm/headsmp-brcmstb.S b/arch/arm/mach-bcm/headsmp-brcmstb.S
deleted file mode 100644
index 199c1ea..0000000
--- a/arch/arm/mach-bcm/headsmp-brcmstb.S
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * SMP boot code for secondary CPUs
- * Based on arch/arm/mach-tegra/headsmp.S
- *
- * Copyright (C) 2010 NVIDIA, Inc.
- * Copyright (C) 2013-2014 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <asm/assembler.h>
-#include <linux/linkage.h>
-#include <linux/init.h>
-
- .section ".text.head", "ax"
-
-ENTRY(brcmstb_secondary_startup)
- /*
- * Ensure CPU is in a sane state by disabling all IRQs and switching
- * into SVC mode.
- */
- setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r0
-
- bl v7_invalidate_l1
- b secondary_startup
-ENDPROC(brcmstb_secondary_startup)
diff --git a/arch/arm/mach-bcm/platsmp-brcmstb.c b/arch/arm/mach-bcm/platsmp-brcmstb.c
index e209e6f..44d6bddf 100644
--- a/arch/arm/mach-bcm/platsmp-brcmstb.c
+++ b/arch/arm/mach-bcm/platsmp-brcmstb.c
@@ -30,8 +30,6 @@
#include <asm/mach-types.h>
#include <asm/smp_plat.h>
-#include "brcmstb.h"
-
enum {
ZONE_MAN_CLKEN_MASK = BIT(0),
ZONE_MAN_RESET_CNTL_MASK = BIT(1),
@@ -153,7 +151,7 @@ static void brcmstb_cpu_boot(u32 cpu)
* Set the reset vector to point to the secondary_startup
* routine
*/
- cpu_set_boot_addr(cpu, virt_to_phys(brcmstb_secondary_startup));
+ cpu_set_boot_addr(cpu, virt_to_phys(secondary_startup));
/* Unhalt the cpu */
cpu_rst_cfg_set(cpu, 0);
diff --git a/arch/arm/mach-berlin/headsmp.S b/arch/arm/mach-berlin/headsmp.S
index 4a4c56a..dc82a34 100644
--- a/arch/arm/mach-berlin/headsmp.S
+++ b/arch/arm/mach-berlin/headsmp.S
@@ -12,12 +12,6 @@
#include <linux/init.h>
#include <asm/assembler.h>
-ENTRY(berlin_secondary_startup)
- ARM_BE8(setend be)
- bl v7_invalidate_l1
- b secondary_startup
-ENDPROC(berlin_secondary_startup)
-
/*
* If the following instruction is set in the reset exception vector, CPUs
* will fetch the value of the software reset address vector when being
diff --git a/arch/arm/mach-berlin/platsmp.c b/arch/arm/mach-berlin/platsmp.c
index 702e798..34a3753 100644
--- a/arch/arm/mach-berlin/platsmp.c
+++ b/arch/arm/mach-berlin/platsmp.c
@@ -22,7 +22,6 @@
#define RESET_VECT 0x00
#define SW_RESET_ADDR 0x94
-extern void berlin_secondary_startup(void);
extern u32 boot_inst;
static void __iomem *cpu_ctrl;
@@ -85,7 +84,7 @@ static void __init berlin_smp_prepare_cpus(unsigned int max_cpus)
* Write the secondary startup address into the SW reset address
* vector. This is used by boot_inst.
*/
- writel(virt_to_phys(berlin_secondary_startup), vectors_base + SW_RESET_ADDR);
+ writel(virt_to_phys(secondary_startup), vectors_base + SW_RESET_ADDR);
iounmap(vectors_base);
unmap_scu:
diff --git a/arch/arm/mach-hisi/Makefile b/arch/arm/mach-hisi/Makefile
index 6b7b303..659db19 100644
--- a/arch/arm/mach-hisi/Makefile
+++ b/arch/arm/mach-hisi/Makefile
@@ -6,4 +6,4 @@ CFLAGS_platmcpm.o := -march=armv7-a
obj-y += hisilicon.o
obj-$(CONFIG_MCPM) += platmcpm.o
-obj-$(CONFIG_SMP) += platsmp.o hotplug.o headsmp.o
+obj-$(CONFIG_SMP) += platsmp.o hotplug.o
diff --git a/arch/arm/mach-hisi/core.h b/arch/arm/mach-hisi/core.h
index 92a682d..c7648ef 100644
--- a/arch/arm/mach-hisi/core.h
+++ b/arch/arm/mach-hisi/core.h
@@ -12,7 +12,6 @@ extern void hi3xxx_cpu_die(unsigned int cpu);
extern int hi3xxx_cpu_kill(unsigned int cpu);
extern void hi3xxx_set_cpu(int cpu, bool enable);
-extern void hisi_secondary_startup(void);
extern struct smp_operations hix5hd2_smp_ops;
extern void hix5hd2_set_cpu(int cpu, bool enable);
extern void hix5hd2_cpu_die(unsigned int cpu);
diff --git a/arch/arm/mach-hisi/headsmp.S b/arch/arm/mach-hisi/headsmp.S
deleted file mode 100644
index 81e35b1..0000000
--- a/arch/arm/mach-hisi/headsmp.S
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * Copyright (c) 2014 Hisilicon Limited.
- * Copyright (c) 2014 Linaro Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/linkage.h>
-#include <linux/init.h>
-
- __CPUINIT
-
-ENTRY(hisi_secondary_startup)
- bl v7_invalidate_l1
- b secondary_startup
diff --git a/arch/arm/mach-hisi/platsmp.c b/arch/arm/mach-hisi/platsmp.c
index 8880c8e..5174412 100644
--- a/arch/arm/mach-hisi/platsmp.c
+++ b/arch/arm/mach-hisi/platsmp.c
@@ -118,7 +118,7 @@ static int hix5hd2_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
phys_addr_t jumpaddr;
- jumpaddr = virt_to_phys(hisi_secondary_startup);
+ jumpaddr = virt_to_phys(secondary_startup);
hix5hd2_set_scu_boot_addr(HIX5HD2_BOOT_ADDRESS, jumpaddr);
hix5hd2_set_cpu(cpu, true);
arch_send_wakeup_ipi_mask(cpumask_of(cpu));
@@ -156,7 +156,7 @@ static int hip01_boot_secondary(unsigned int cpu, struct task_struct *idle)
struct device_node *node;
- jumpaddr = virt_to_phys(hisi_secondary_startup);
+ jumpaddr = virt_to_phys(secondary_startup);
hip01_set_boot_addr(HIP01_BOOT_ADDRESS, jumpaddr);
node = of_find_compatible_node(NULL, NULL, "hisilicon,hip01-sysctrl");
diff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S
index de5047c..b5e9768 100644
--- a/arch/arm/mach-imx/headsmp.S
+++ b/arch/arm/mach-imx/headsmp.S
@@ -25,7 +25,6 @@ diag_reg_offset:
.endm
ENTRY(v7_secondary_startup)
- bl v7_invalidate_l1
set_diag_reg
b secondary_startup
ENDPROC(v7_secondary_startup)
diff --git a/arch/arm/mach-mvebu/headsmp-a9.S b/arch/arm/mach-mvebu/headsmp-a9.S
index 08d5ed4..48e4c4b 100644
--- a/arch/arm/mach-mvebu/headsmp-a9.S
+++ b/arch/arm/mach-mvebu/headsmp-a9.S
@@ -21,7 +21,6 @@
ENTRY(mvebu_cortex_a9_secondary_startup)
ARM_BE8(setend be)
- bl v7_invalidate_l1
bl armada_38x_scu_power_up
b secondary_startup
ENDPROC(mvebu_cortex_a9_secondary_startup)
diff --git a/arch/arm/mach-prima2/headsmp.S b/arch/arm/mach-prima2/headsmp.S
index d86fe33..209d9fc 100644
--- a/arch/arm/mach-prima2/headsmp.S
+++ b/arch/arm/mach-prima2/headsmp.S
@@ -15,7 +15,6 @@
* ready for them to initialise.
*/
ENTRY(sirfsoc_secondary_startup)
- bl v7_invalidate_l1
mrc p15, 0, r0, c0, c0, 5
and r0, r0, #15
adr r4, 1f
diff --git a/arch/arm/mach-rockchip/core.h b/arch/arm/mach-rockchip/core.h
index 39bca96..492c048 100644
--- a/arch/arm/mach-rockchip/core.h
+++ b/arch/arm/mach-rockchip/core.h
@@ -17,4 +17,3 @@ extern char rockchip_secondary_trampoline;
extern char rockchip_secondary_trampoline_end;
extern unsigned long rockchip_boot_fn;
-extern void rockchip_secondary_startup(void);
diff --git a/arch/arm/mach-rockchip/headsmp.S b/arch/arm/mach-rockchip/headsmp.S
index 46c22de..d69708b 100644
--- a/arch/arm/mach-rockchip/headsmp.S
+++ b/arch/arm/mach-rockchip/headsmp.S
@@ -15,14 +15,6 @@
#include <linux/linkage.h>
#include <linux/init.h>
-ENTRY(rockchip_secondary_startup)
- mrc p15, 0, r0, c0, c0, 0 @ read main ID register
- ldr r1, =0x00000c09 @ Cortex-A9 primary part number
- teq r0, r1
- beq v7_invalidate_l1
- b secondary_startup
-ENDPROC(rockchip_secondary_startup)
-
ENTRY(rockchip_secondary_trampoline)
ldr pc, 1f
ENDPROC(rockchip_secondary_trampoline)
diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
index 5b4ca3c..2e6ab67 100644
--- a/arch/arm/mach-rockchip/platsmp.c
+++ b/arch/arm/mach-rockchip/platsmp.c
@@ -149,8 +149,7 @@ static int __cpuinit rockchip_boot_secondary(unsigned int cpu,
* sram_base_addr + 8: start address for pc
* */
udelay(10);
- writel(virt_to_phys(rockchip_secondary_startup),
- sram_base_addr + 8);
+ writel(virt_to_phys(secondary_startup), sram_base_addr + 8);
writel(0xDEADBEAF, sram_base_addr + 4);
dsb_sev();
}
@@ -189,7 +188,7 @@ static int __init rockchip_smp_prepare_sram(struct device_node *node)
}
/* set the boot function for the sram code */
- rockchip_boot_fn = virt_to_phys(rockchip_secondary_startup);
+ rockchip_boot_fn = virt_to_phys(secondary_startup);
/* copy the trampoline to sram, that runs during startup of the core */
memcpy(sram_base_addr, &rockchip_secondary_trampoline, trampoline_sz);
diff --git a/arch/arm/mach-shmobile/common.h b/arch/arm/mach-shmobile/common.h
index afc60ba..476092b 100644
--- a/arch/arm/mach-shmobile/common.h
+++ b/arch/arm/mach-shmobile/common.h
@@ -14,7 +14,6 @@ extern void shmobile_smp_sleep(void);
extern void shmobile_smp_hook(unsigned int cpu, unsigned long fn,
unsigned long arg);
extern int shmobile_smp_cpu_disable(unsigned int cpu);
-extern void shmobile_invalidate_start(void);
extern void shmobile_boot_scu(void);
extern void shmobile_smp_scu_prepare_cpus(unsigned int max_cpus);
extern void shmobile_smp_scu_cpu_die(unsigned int cpu);
diff --git a/arch/arm/mach-shmobile/headsmp-scu.S b/arch/arm/mach-shmobile/headsmp-scu.S
index 69df8bf..fa5248c 100644
--- a/arch/arm/mach-shmobile/headsmp-scu.S
+++ b/arch/arm/mach-shmobile/headsmp-scu.S
@@ -22,7 +22,7 @@
* Boot code for secondary CPUs.
*
* First we turn on L1 cache coherency for our CPU. Then we jump to
- * shmobile_invalidate_start that invalidates the cache and hands over control
+ * secondary_startup that invalidates the cache and hands over control
* to the common ARM startup code.
*/
ENTRY(shmobile_boot_scu)
@@ -36,7 +36,7 @@ ENTRY(shmobile_boot_scu)
bic r2, r2, r3 @ Clear bits of our CPU (Run Mode)
str r2, [r0, #8] @ write back
- b shmobile_invalidate_start
+ b secondary_startup
ENDPROC(shmobile_boot_scu)
.text
diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S
index 50c4915..330c1fc 100644
--- a/arch/arm/mach-shmobile/headsmp.S
+++ b/arch/arm/mach-shmobile/headsmp.S
@@ -16,13 +16,6 @@
#include <asm/assembler.h>
#include <asm/memory.h>
-#ifdef CONFIG_SMP
-ENTRY(shmobile_invalidate_start)
- bl v7_invalidate_l1
- b secondary_startup
-ENDPROC(shmobile_invalidate_start)
-#endif
-
/*
* Reset vector for secondary CPUs.
* This will be mapped at address 0 by SBAR register.
diff --git a/arch/arm/mach-shmobile/platsmp-apmu.c b/arch/arm/mach-shmobile/platsmp-apmu.c
index f483b56..b0790fc 100644
--- a/arch/arm/mach-shmobile/platsmp-apmu.c
+++ b/arch/arm/mach-shmobile/platsmp-apmu.c
@@ -133,7 +133,7 @@ void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus,
int shmobile_smp_apmu_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
/* For this particular CPU register boot vector */
- shmobile_smp_hook(cpu, virt_to_phys(shmobile_invalidate_start), 0);
+ shmobile_smp_hook(cpu, virt_to_phys(secondary_startup), 0);
return apmu_wrap(cpu, apmu_power_on);
}
diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h
index a0f3b1c..767c09e 100644
--- a/arch/arm/mach-socfpga/core.h
+++ b/arch/arm/mach-socfpga/core.h
@@ -31,7 +31,6 @@
#define RSTMGR_MPUMODRST_CPU1 0x2 /* CPU1 Reset */
-extern void socfpga_secondary_startup(void);
extern void __iomem *socfpga_scu_base_addr;
extern void socfpga_init_clocks(void);
diff --git a/arch/arm/mach-socfpga/headsmp.S b/arch/arm/mach-socfpga/headsmp.S
index f65ea0a..5bb0164 100644
--- a/arch/arm/mach-socfpga/headsmp.S
+++ b/arch/arm/mach-socfpga/headsmp.S
@@ -30,8 +30,3 @@ ENTRY(secondary_trampoline)
1: .long .
.long socfpga_cpu1start_addr
ENTRY(secondary_trampoline_end)
-
-ENTRY(socfpga_secondary_startup)
- bl v7_invalidate_l1
- b secondary_startup
-ENDPROC(socfpga_secondary_startup)
diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c
index c64d89b..79c5336 100644
--- a/arch/arm/mach-socfpga/platsmp.c
+++ b/arch/arm/mach-socfpga/platsmp.c
@@ -40,7 +40,7 @@ static int socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
- writel(virt_to_phys(socfpga_secondary_startup),
+ writel(virt_to_phys(secondary_startup),
sys_manager_base_addr + (socfpga_cpu1start_addr & 0x000000ff));
flush_cache_all();
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index e48a744..fffad24 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -19,7 +19,7 @@ obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pm-tegra30.o
ifeq ($(CONFIG_CPU_IDLE),y)
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += cpuidle-tegra30.o
endif
-obj-$(CONFIG_SMP) += platsmp.o headsmp.o
+obj-$(CONFIG_SMP) += platsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
obj-$(CONFIG_ARCH_TEGRA_114_SOC) += sleep-tegra30.o
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
deleted file mode 100644
index 2072e73..0000000
--- a/arch/arm/mach-tegra/headsmp.S
+++ /dev/null
@@ -1,12 +0,0 @@
-#include <linux/linkage.h>
-#include <linux/init.h>
-
-#include "sleep.h"
-
- .section ".text.head", "ax"
-
-ENTRY(tegra_secondary_startup)
- check_cpu_part_num 0xc09, r8, r9
- bleq v7_invalidate_l1
- b secondary_startup
-ENDPROC(tegra_secondary_startup)
diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c
index 894c5c4..6fd9db5 100644
--- a/arch/arm/mach-tegra/reset.c
+++ b/arch/arm/mach-tegra/reset.c
@@ -94,7 +94,7 @@ void __init tegra_cpu_reset_handler_init(void)
__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] =
*((u32 *)cpu_possible_mask);
__tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_SECONDARY] =
- virt_to_phys((void *)tegra_secondary_startup);
+ virt_to_phys((void *)secondary_startup);
#endif
#ifdef CONFIG_PM_SLEEP
diff --git a/arch/arm/mach-tegra/reset.h b/arch/arm/mach-tegra/reset.h
index 29c3dec..9c479c7 100644
--- a/arch/arm/mach-tegra/reset.h
+++ b/arch/arm/mach-tegra/reset.h
@@ -37,7 +37,6 @@ void __tegra_cpu_reset_handler_start(void);
void __tegra_cpu_reset_handler(void);
void __tegra20_cpu1_resettable_status_offset(void);
void __tegra_cpu_reset_handler_end(void);
-void tegra_secondary_startup(void);
#ifdef CONFIG_PM_SLEEP
#define tegra_cpu_lp1_mask \
diff --git a/arch/arm/mach-zynq/common.h b/arch/arm/mach-zynq/common.h
index 382c60e..7038cae 100644
--- a/arch/arm/mach-zynq/common.h
+++ b/arch/arm/mach-zynq/common.h
@@ -17,8 +17,6 @@
#ifndef __MACH_ZYNQ_COMMON_H__
#define __MACH_ZYNQ_COMMON_H__
-void zynq_secondary_startup(void);
-
extern int zynq_slcr_init(void);
extern int zynq_early_slcr_init(void);
extern void zynq_slcr_system_reset(void);
diff --git a/arch/arm/mach-zynq/headsmp.S b/arch/arm/mach-zynq/headsmp.S
index dd8c071..045c727 100644
--- a/arch/arm/mach-zynq/headsmp.S
+++ b/arch/arm/mach-zynq/headsmp.S
@@ -22,8 +22,3 @@ zynq_secondary_trampoline_jump:
.globl zynq_secondary_trampoline_end
zynq_secondary_trampoline_end:
ENDPROC(zynq_secondary_trampoline)
-
-ENTRY(zynq_secondary_startup)
- bl v7_invalidate_l1
- b secondary_startup
-ENDPROC(zynq_secondary_startup)
diff --git a/arch/arm/mach-zynq/platsmp.c b/arch/arm/mach-zynq/platsmp.c
index 52d768f..f66816c 100644
--- a/arch/arm/mach-zynq/platsmp.c
+++ b/arch/arm/mach-zynq/platsmp.c
@@ -87,10 +87,9 @@ int zynq_cpun_start(u32 address, int cpu)
}
EXPORT_SYMBOL(zynq_cpun_start);
-static int zynq_boot_secondary(unsigned int cpu,
- struct task_struct *idle)
+static int zynq_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
- return zynq_cpun_start(virt_to_phys(zynq_secondary_startup), cpu);
+ return zynq_cpun_start(virt_to_phys(secondary_startup), cpu);
}
/*
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 3d1054f..75ae721 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -336,7 +336,7 @@ __v7_pj4b_setup:
__v7_setup:
adr r12, __v7_setup_stack @ the local stack
stmia r12, {r0-r5, r7, r9, r11, lr}
- bl v7_flush_dcache_louis
+ bl v7_invalidate_l1
ldmia r12, {r0-r5, r7, r9, r11, lr}
mrc p15, 0, r0, c0, c0, 0 @ read main ID register
--
1.7.9.5
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH 3/3] ARM: v7 setup function should invalidate L1 cache
2015-08-15 0:32 ` [PATCH 3/3] ARM: v7 setup function should invalidate L1 cache Alexander Kochetkov
@ 2015-08-15 8:00 ` Russell King - ARM Linux
2015-08-15 10:50 ` Alexander Kochetkov
0 siblings, 1 reply; 11+ messages in thread
From: Russell King - ARM Linux @ 2015-08-15 8:00 UTC (permalink / raw)
To: Alexander Kochetkov; +Cc: stable
On Sat, Aug 15, 2015 at 04:32:37AM +0400, Alexander Kochetkov wrote:
> From: Russell King <rmk+kernel@arm.linux.org.uk>
>
> commit 02b4e2756e01c623cc4dbceae4b07be75252db5b upstream.
>
> All ARMv5 and older CPUs invalidate their caches in the early assembly
> setup function, prior to enabling the MMU. This is because the L1
> cache should not contain any data relevant to the execution of the
> kernel at this point; all data should have been flushed out to memory.
You also need bac51ad9d14f6baed3730ef53bedc1eb2238563a together with
this, which has a small fix for this patch.
--
FTTC broadband for 0.8mile line: currently at 10.5Mbps down 400kbps up
according to speedtest.net.
^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH 3/3] ARM: v7 setup function should invalidate L1 cache
2015-08-15 8:00 ` Russell King - ARM Linux
@ 2015-08-15 10:50 ` Alexander Kochetkov
2015-08-15 10:50 ` [PATCH] ARM: invalidate L1 before enabling coherency Alexander Kochetkov
0 siblings, 1 reply; 11+ messages in thread
From: Alexander Kochetkov @ 2015-08-15 10:50 UTC (permalink / raw)
To: linux, stable; +Cc: Alexander Kochetkov
Russell King - ARM Linux <linux@arm.linux.org.uk> *
> You also need bac51ad9d14f6baed3730ef53bedc1eb2238563a together with
> this, which has a small fix for this patch.
Here is bac51ad9d14f6baed3730ef53bedc1eb2238563a backport for 4.1-stable.
Tested on rk3188, all looks great.
Thank you, Russell, for pointing that.
Alexander.
Russell King (1):
ARM: invalidate L1 before enabling coherency
arch/arm/mm/proc-v7.S | 14 +++++++++-----
1 file changed, 9 insertions(+), 5 deletions(-)
--
1.7.9.5
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH] ARM: invalidate L1 before enabling coherency
2015-08-15 10:50 ` Alexander Kochetkov
@ 2015-08-15 10:50 ` Alexander Kochetkov
0 siblings, 0 replies; 11+ messages in thread
From: Alexander Kochetkov @ 2015-08-15 10:50 UTC (permalink / raw)
To: linux, stable; +Cc: Russell King
From: Russell King <rmk+kernel@arm.linux.org.uk>
commit bac51ad9d14f6baed3730ef53bedc1eb2238563a upstream.
We must invalidate the L1 cache before enabling coherency, otherwise
secondary CPUs can inject invalid cache lines into the coherent CPU
cluster, which could then be migrated to other CPUs. This fixes a
recent regression with SoCFPGA randomly failing to boot.
Fixes: 02b4e2756e01 ("ARM: v7 setup function should invalidate L1 cache")
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
arch/arm/mm/proc-v7.S | 14 +++++++++-----
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 75ae721..7911f14 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -268,7 +268,10 @@ __v7_ca15mp_setup:
__v7_b15mp_setup:
__v7_ca17mp_setup:
mov r10, #0
-1:
+1: adr r12, __v7_setup_stack @ the local stack
+ stmia r12, {r0-r5, lr} @ v7_invalidate_l1 touches r0-r6
+ bl v7_invalidate_l1
+ ldmia r12, {r0-r5, lr}
#ifdef CONFIG_SMP
ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
ALT_UP(mov r0, #(1 << 6)) @ fake it for UP
@@ -277,7 +280,7 @@ __v7_ca17mp_setup:
orreq r0, r0, r10 @ Enable CPU-specific SMP bits
mcreq p15, 0, r0, c1, c0, 1
#endif
- b __v7_setup
+ b __v7_setup_cont
__v7_pj4b_setup:
#ifdef CONFIG_CPU_PJ4B
@@ -335,10 +338,11 @@ __v7_pj4b_setup:
__v7_setup:
adr r12, __v7_setup_stack @ the local stack
- stmia r12, {r0-r5, r7, r9, r11, lr}
+ stmia r12, {r0-r5, lr} @ v7_invalidate_l1 touches r0-r6
bl v7_invalidate_l1
- ldmia r12, {r0-r5, r7, r9, r11, lr}
+ ldmia r12, {r0-r5, lr}
+__v7_setup_cont:
mrc p15, 0, r0, c0, c0, 0 @ read main ID register
and r10, r0, #0xff000000 @ ARM?
teq r10, #0x41000000
@@ -460,7 +464,7 @@ ENDPROC(__v7_setup)
.align 2
__v7_setup_stack:
- .space 4 * 11 @ 11 registers
+ .space 4 * 7 @ 12 registers
__INITDATA
--
1.7.9.5
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH 1/3] ARM: 8385/1: VDSO: group link options
2015-08-15 0:32 ` [PATCH 1/3] ARM: 8385/1: VDSO: group link options Alexander Kochetkov
@ 2015-08-19 21:05 ` Nathan Lynch
0 siblings, 0 replies; 11+ messages in thread
From: Nathan Lynch @ 2015-08-19 21:05 UTC (permalink / raw)
To: Alexander Kochetkov; +Cc: stable, Russell King
On 08/14/2015 07:32 PM, Alexander Kochetkov wrote:
> From: Nathan Lynch <nathan_lynch@mentor.com>
>
> commit d33ce23b2160d26b27a47092da5d556b5b11a12a upstream.
>
> Currently the VDSO's link options are kind of a mess spread between
>
> ccflags-y and cmd_vdsold. Collect linker directives into one
> variable, VDSO_LDFLAGS, and use that in cmd_vdsold.
>
> Signed-off-by: Nathan Lynch <nathan_lynch@mentor.com>
> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Since they fix a build regression with certain toolchains[*], I agree
with putting the ARM VDSO patches (#1 and #2 from this thread) into
4.1-stable, as long as 3473f26592c1c "ARM: 8405/1: VDSO: fix regression
with toolchains lacking ld.bfd executable" is applied immediately
afterward, since it fixes a problem introduced by #2.
[*] Toolchains built by the Angstrom distribution from Linaro sources,
not current binary toolchains as distributed by Linaro, as implied in
the cover letter. One change Angstrom makes is the choice of default
linker, which is what exposed the problem in the first place.
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 0/3] Patches to apply to v4.1-stable
2015-08-15 0:32 [PATCH 0/3] Patches to apply to v4.1-stable Alexander Kochetkov
` (2 preceding siblings ...)
2015-08-15 0:32 ` [PATCH 3/3] ARM: v7 setup function should invalidate L1 cache Alexander Kochetkov
@ 2015-09-11 6:11 ` Greg KH
2015-09-12 11:59 ` Alexander Kochetkov
3 siblings, 1 reply; 11+ messages in thread
From: Greg KH @ 2015-09-11 6:11 UTC (permalink / raw)
To: Alexander Kochetkov; +Cc: stable
On Sat, Aug 15, 2015 at 04:32:34AM +0400, Alexander Kochetkov wrote:
> Hi Greg,
>
> Please apply the following three patches to v4.1-stable.
> They fixes regressions introduced somethere between 3.18.20 and 4.1.5.
All now applied, thanks.
greg k-h
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 0/3] Patches to apply to v4.1-stable
2015-09-11 6:11 ` [PATCH 0/3] Patches to apply to v4.1-stable Greg KH
@ 2015-09-12 11:59 ` Alexander Kochetkov
2015-09-12 15:51 ` Greg KH
0 siblings, 1 reply; 11+ messages in thread
From: Alexander Kochetkov @ 2015-09-12 11:59 UTC (permalink / raw)
To: Greg KH; +Cc: stable, nathan_lynch
> 11 september. 2015 г., 9:11, Greg KH <greg@kroah.com> *:
>
> All now applied, thanks.
>
> greg k-h
Hello Geg,
Thank you for your hard work!
Please apply also 3473f26592c1c "ARM: 8405/1: VDSO: fix regression
with toolchains lacking ld.bfd executable» on top of already applied VDSO patches.
Here is comment from Nathan Lynch:
> Since they fix a build regression with certain toolchains[*], I agree
> with putting the ARM VDSO patches (#1 and #2 from this thread) into
> 4.1-stable, as long as 3473f26592c1c "ARM: 8405/1: VDSO: fix regression
> with toolchains lacking ld.bfd executable" is applied immediately
> afterward, since it fixes a problem introduced by #2.
Thank you,
Alexander.
You can read whole thread here:
http://thread.gmane.org/gmane.linux.kernel.stable/146826
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 0/3] Patches to apply to v4.1-stable
2015-09-12 11:59 ` Alexander Kochetkov
@ 2015-09-12 15:51 ` Greg KH
0 siblings, 0 replies; 11+ messages in thread
From: Greg KH @ 2015-09-12 15:51 UTC (permalink / raw)
To: Alexander Kochetkov; +Cc: stable, nathan_lynch
On Sat, Sep 12, 2015 at 02:59:50PM +0300, Alexander Kochetkov wrote:
>
> > 11 september. 2015 г., 9:11, Greg KH <greg@kroah.com> *:
> >
> > All now applied, thanks.
> >
> > greg k-h
>
> Hello Geg,
>
> Thank you for your hard work!
>
> Please apply also 3473f26592c1c "ARM: 8405/1: VDSO: fix regression
> with toolchains lacking ld.bfd executable» on top of already applied VDSO patches.
>
> Here is comment from Nathan Lynch:
> > Since they fix a build regression with certain toolchains[*], I agree
> > with putting the ARM VDSO patches (#1 and #2 from this thread) into
> > 4.1-stable, as long as 3473f26592c1c "ARM: 8405/1: VDSO: fix regression
> > with toolchains lacking ld.bfd executable" is applied immediately
> > afterward, since it fixes a problem introduced by #2.
Now added, thanks.
greg k-h
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2015-09-12 15:51 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2015-08-15 0:32 [PATCH 0/3] Patches to apply to v4.1-stable Alexander Kochetkov
2015-08-15 0:32 ` [PATCH 1/3] ARM: 8385/1: VDSO: group link options Alexander Kochetkov
2015-08-19 21:05 ` Nathan Lynch
2015-08-15 0:32 ` [PATCH 2/3] ARM: 8384/1: VDSO: force use of BFD linker Alexander Kochetkov
2015-08-15 0:32 ` [PATCH 3/3] ARM: v7 setup function should invalidate L1 cache Alexander Kochetkov
2015-08-15 8:00 ` Russell King - ARM Linux
2015-08-15 10:50 ` Alexander Kochetkov
2015-08-15 10:50 ` [PATCH] ARM: invalidate L1 before enabling coherency Alexander Kochetkov
2015-09-11 6:11 ` [PATCH 0/3] Patches to apply to v4.1-stable Greg KH
2015-09-12 11:59 ` Alexander Kochetkov
2015-09-12 15:51 ` Greg KH
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