From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from wtarreau.pck.nerim.net ([62.212.114.60]:12935 "EHLO 1wt.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750750AbbIOHn7 (ORCPT ); Tue, 15 Sep 2015 03:43:59 -0400 Date: Tue, 15 Sep 2015 09:43:53 +0200 From: Willy Tarreau To: Ben Hutchings Cc: linux-kernel@vger.kernel.org, stable@vger.kernel.org, Ralf Baechle Subject: Re: [PATCH 2.6.32 35/62] MIPS: Fix cpu_has_mips_r2_exec_hazard. Message-ID: <20150915074353.GD29318@1wt.eu> References: <20150912225608.071797495@1wt.eu> <1442286145.29883.8.camel@decadent.org.uk> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1442286145.29883.8.camel@decadent.org.uk> Sender: stable-owner@vger.kernel.org List-ID: On Tue, Sep 15, 2015 at 04:02:25AM +0100, Ben Hutchings wrote: > On Sun, 2015-09-13 at 00:56 +0200, Willy Tarreau wrote: > > 2.6.32-longterm review patch. If anyone has any objections, please let me know. > > > > ------------------ > > > > From: Ralf Baechle > > > > commit 9cdf30bd3bac697fc533988f44a117434a858f69 upstream. > > > > Returns a non-zero value if the current processor implementation requires > > an IHB instruction to deal with an instruction hazard as per MIPS R2 > > architecture specification, zero otherwise. > > > > For a discussion, see http://patchwork.linux-mips.org/patch/9539/. > > > > Signed-off-by: Ralf Baechle > > [bwh: Backported to 3.2: trim the CPU type list] > > Signed-off-by: Ben Hutchings > > (cherry picked from commit 8feb2a714b3478b2cde5c576fd9f47ef44b60e8d) > > > > Signed-off-by: Willy Tarreau > > --- > > arch/mips/include/asm/cpu-features.h | 26 +++++++++++++++++++++++++- > > 1 file changed, 25 insertions(+), 1 deletion(-) > > > > diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h > > index 1f4df64..a3dbb59 100644 > > --- a/arch/mips/include/asm/cpu-features.h > > +++ b/arch/mips/include/asm/cpu-features.h > > @@ -150,8 +150,32 @@ > > #define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \ > > cpu_has_mips64r1 | cpu_has_mips64r2) > > > > +/* > > + * cpu_has_mips_r2_exec_hazard - return if IHB is required on current processor > > + * > > + * Returns non-zero value if the current processor implementation requires > > + * an IHB instruction to deal with an instruction hazard as per MIPS R2 > > + * architecture specification, zero otherwise. > > + */ > > #ifndef cpu_has_mips_r2_exec_hazard > > -#define cpu_has_mips_r2_exec_hazard cpu_has_mips_r2 > > +#define cpu_has_mips_r2_exec_hazard \ > > +({ \ > > + int __res; \ > > + \ > > + switch (current_cpu_type()) { \ > > + case CPU_74K: \ > > + case CPU_CAVIUM_OCTEON: \ > > + case CPU_CAVIUM_OCTEON_PLUS: \ > > + case CPU_CAVIUM_OCTEON2: \ > [...] > > These last two constants aren't defined in 2.6.32, so they would need to > be removed too. But I don't think this is needed at all. Ah thanks, I only built x86_64 and i386. OK I'm dropping the whole patch. Thanks, Willy