From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linuxfoundation.org ([140.211.169.12]:34257 "EHLO mail.linuxfoundation.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756440AbbJAJXl (ORCPT ); Thu, 1 Oct 2015 05:23:41 -0400 From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Matan Barak , Carol L Soto , "David S. Miller" Subject: [PATCH 4.2 30/30] net/mlx4_core: Capping number of requested MSIXs to MAX_MSIX Date: Thu, 1 Oct 2015 11:21:52 +0200 Message-Id: <20151001092039.507277344@linuxfoundation.org> In-Reply-To: <20151001092038.213304276@linuxfoundation.org> References: <20151001092038.213304276@linuxfoundation.org> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15 Sender: stable-owner@vger.kernel.org List-ID: 4.2-stable review patch. If anyone has any objections, please let me know. ------------------ From: Carol L Soto [ Upstream commit 9293267a3e2a7a2555d8ddc8f9301525e5b03b1b ] We currently manage IRQs in pool_bm which is a bit field of MAX_MSIX bits. Thus, allocating more than MAX_MSIX interrupts can't be managed in pool_bm. Fixing this by capping number of requested MSIXs to MAX_MSIX. Signed-off-by: Matan Barak Signed-off-by: Carol L Soto Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- drivers/net/ethernet/mellanox/mlx4/main.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) --- a/drivers/net/ethernet/mellanox/mlx4/main.c +++ b/drivers/net/ethernet/mellanox/mlx4/main.c @@ -2654,9 +2654,14 @@ static void mlx4_enable_msi_x(struct mlx if (msi_x) { int nreq = dev->caps.num_ports * num_online_cpus() + 1; + bool shared_ports = false; nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs, nreq); + if (nreq > MAX_MSIX) { + nreq = MAX_MSIX; + shared_ports = true; + } entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL); if (!entries) @@ -2679,6 +2684,9 @@ static void mlx4_enable_msi_x(struct mlx bitmap_zero(priv->eq_table.eq[MLX4_EQ_ASYNC].actv_ports.ports, dev->caps.num_ports); + if (MLX4_IS_LEGACY_EQ_MODE(dev->caps)) + shared_ports = true; + for (i = 0; i < dev->caps.num_comp_vectors + 1; i++) { if (i == MLX4_EQ_ASYNC) continue; @@ -2686,7 +2694,7 @@ static void mlx4_enable_msi_x(struct mlx priv->eq_table.eq[i].irq = entries[i + 1 - !!(i > MLX4_EQ_ASYNC)].vector; - if (MLX4_IS_LEGACY_EQ_MODE(dev->caps)) { + if (shared_ports) { bitmap_fill(priv->eq_table.eq[i].actv_ports.ports, dev->caps.num_ports); /* We don't set affinity hint when there