From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com ([192.55.52.88]:35386 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753780AbbJHISs (ORCPT ); Thu, 8 Oct 2015 04:18:48 -0400 Date: Thu, 8 Oct 2015 11:18:44 +0300 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Daniel Vetter Cc: intel-gfx@lists.freedesktop.org, Nick Bowler , stable@vger.kernel.org Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915: Restore lost DPLL register write on gen2-4 Message-ID: <20151008081844.GS26517@intel.com> References: <1444244905-27894-1-git-send-email-ville.syrjala@linux.intel.com> <20151008081730.GZ3383@phenom.ffwll.local> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20151008081730.GZ3383@phenom.ffwll.local> Sender: stable-owner@vger.kernel.org List-ID: On Thu, Oct 08, 2015 at 10:17:30AM +0200, Daniel Vetter wrote: > On Wed, Oct 07, 2015 at 10:08:24PM +0300, ville.syrjala@linux.intel.com wrote: > > From: Ville Syrj�l� > > > > We accidentally lost the initial DPLL register write in > > 1c4e02746147 drm/i915: Fix DVO 2x clock enable on 830M > > > > The "three times for luck" hack probably saved us from a total > > disaster. But anyway, bring the initial write back so that the > > code actually makes some sense. > > > > Cc: stable@vger.kernel.org > > Cc: Nick Bowler > Reported-and-tested-by: Nick Bowler > References: http://lists.freedesktop.org/archives/intel-gfx/2015-October/077463.html > > > Signed-off-by: Ville Syrj�l� > > --- > > drivers/gpu/drm/i915/intel_display.c | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > > index 147e700..f4fdff9 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -1743,6 +1743,8 @@ static void i9xx_enable_pll(struct intel_crtc *crtc) > > I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); > > Don't we also need a POSTING_READ here to make sure the two-step 2x mode > sequence is still followed? We don't do write combining on registers, and there are no shadow register type of things to consider in this case either. > > With that addressed Reviewed-by: Daniel Vetter > > } > > > > + I915_WRITE(reg, dpll); > > + > > /* Wait for the clocks to stabilize. */ > > POSTING_READ(reg); > > udelay(150); > > -- > > 2.4.9 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Daniel Vetter > Software Engineer, Intel Corporation > http://blog.ffwll.ch -- Ville Syrj�l� Intel OTC