From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wi0-f169.google.com ([209.85.212.169]:35930 "EHLO mail-wi0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752922AbbJMNxi (ORCPT ); Tue, 13 Oct 2015 09:53:38 -0400 Received: by wicgb1 with SMTP id gb1so190051533wic.1 for ; Tue, 13 Oct 2015 06:53:37 -0700 (PDT) Date: Tue, 13 Oct 2015 15:56:04 +0200 From: Daniel Vetter To: Jani Nikula Cc: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= , Daniel Vetter , Nick Bowler , intel-gfx@lists.freedesktop.org, stable@vger.kernel.org Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915: Restore lost DPLL register write on gen2-4 Message-ID: <20151013135604.GE26718@phenom.ffwll.local> References: <1444244905-27894-1-git-send-email-ville.syrjala@linux.intel.com> <20151008081730.GZ3383@phenom.ffwll.local> <20151008081844.GS26517@intel.com> <87pp0i52ys.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <87pp0i52ys.fsf@intel.com> Sender: stable-owner@vger.kernel.org List-ID: On Tue, Oct 13, 2015 at 04:10:19PM +0300, Jani Nikula wrote: > On Thu, 08 Oct 2015, Ville Syrj�l� wrote: > > On Thu, Oct 08, 2015 at 10:17:30AM +0200, Daniel Vetter wrote: > >> On Wed, Oct 07, 2015 at 10:08:24PM +0300, ville.syrjala@linux.intel.com wrote: > >> > From: Ville Syrj�l� > >> > > >> > We accidentally lost the initial DPLL register write in > >> > 1c4e02746147 drm/i915: Fix DVO 2x clock enable on 830M > >> > > >> > The "three times for luck" hack probably saved us from a total > >> > disaster. But anyway, bring the initial write back so that the > >> > code actually makes some sense. > >> > > >> > Cc: stable@vger.kernel.org > >> > Cc: Nick Bowler > >> Reported-and-tested-by: Nick Bowler > >> References: http://lists.freedesktop.org/archives/intel-gfx/2015-October/077463.html > >> > >> > Signed-off-by: Ville Syrj�l� > >> > --- > >> > drivers/gpu/drm/i915/intel_display.c | 2 ++ > >> > 1 file changed, 2 insertions(+) > >> > > >> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > >> > index 147e700..f4fdff9 100644 > >> > --- a/drivers/gpu/drm/i915/intel_display.c > >> > +++ b/drivers/gpu/drm/i915/intel_display.c > >> > @@ -1743,6 +1743,8 @@ static void i9xx_enable_pll(struct intel_crtc *crtc) > >> > I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); > >> > >> Don't we also need a POSTING_READ here to make sure the two-step 2x mode > >> sequence is still followed? > > > > We don't do write combining on registers, and there are no shadow > > register type of things to consider in this case either. > > > >> > >> With that addressed Reviewed-by: Daniel Vetter > > > Daniel, are you happy with the responses about posting reads, for both > patches? Yeah, acked on irc but forgot to follow up. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch