From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wi0-f175.google.com ([209.85.212.175]:38564 "EHLO mail-wi0-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751957AbbJVNLV (ORCPT ); Thu, 22 Oct 2015 09:11:21 -0400 Received: by wicll6 with SMTP id ll6so118403666wic.1 for ; Thu, 22 Oct 2015 06:11:20 -0700 (PDT) Date: Thu, 22 Oct 2015 15:11:18 +0200 From: Daniel Vetter To: Maarten Lankhorst Cc: intel-gfx@lists.freedesktop.org, stable@vger.kernel.org, Jani Nikula Subject: Re: [Intel-gfx] [PATCH 09/11] drm/i915/skl: Prevent unclaimed register writes on skylake. Message-ID: <20151022131118.GV16848@phenom.ffwll.local> References: <1445514996-18733-1-git-send-email-maarten.lankhorst@linux.intel.com> <1445514996-18733-10-git-send-email-maarten.lankhorst@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1445514996-18733-10-git-send-email-maarten.lankhorst@linux.intel.com> Sender: stable-owner@vger.kernel.org List-ID: On Thu, Oct 22, 2015 at 01:56:34PM +0200, Maarten Lankhorst wrote: > I'm getting unclaimed register writes when checking the WM registers > after the crtc is disabled. So I would imagine those are guarded by > the crtc power well. Fix this by not reading out wm state when the > power well is off. > > Signed-off-by: Maarten Lankhorst > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92181 > Cc: stable@vger.kernel.org Reviewed-by: Daniel Vetter Jani, one for you. -Daniel > --- > drivers/gpu/drm/i915/intel_pm.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 4c1c1bb96a9e..fbc10331055e 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -2833,7 +2833,12 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, > int plane; > u32 val; > > + memset(ddb, 0, sizeof(*ddb)); > + > for_each_pipe(dev_priv, pipe) { > + if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) > + continue; > + > for_each_plane(dev_priv, pipe, plane) { > val = I915_READ(PLANE_BUF_CFG(pipe, plane)); > skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane], > -- > 2.1.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch