Re: "drm/i915: Update CDCLK_FREQ register on BDW after changing cdclk frequency" to 4.4.x as well?

Re: "drm/i915: Update CDCLK_FREQ register on BDW after changing cdclk frequency" to 4.4.x as well?

[Ville Syrjälä]

On Fri, May 27, 2016 at 03:20:04PM +0000, Joakim Tjernlund wrote:
> I see that above patch is in 4.5 but not in 4.4, should it not be in 4.4 as well?
> 
> Link to commit in 4.5
> https://git.kernel.org/cgit/linux/kernel/git/stable/linux-stable.git/commit/?h=linux-4.5.y&id=be19315585fa23cc
> 9a2758e9f29f01b1095e134f

Yeah, looks like the relevant commit went into 4.3, so stable 4.4
should get the fix as well. Cc:ing stable folks...

-- 
Ville Syrj�l�
Intel OTC

Re: "drm/i915: Update CDCLK_FREQ register on BDW after changing cdclk frequency" to 4.4.x as well?

[Greg KH]

On Fri, May 27, 2016 at 07:34:39PM +0300, Ville Syrj�l� wrote:
> On Fri, May 27, 2016 at 03:20:04PM +0000, Joakim Tjernlund wrote:
> > I see that above patch is in 4.5 but not in 4.4, should it not be in 4.4 as well?
> > 
> > Link to commit in 4.5
> > https://git.kernel.org/cgit/linux/kernel/git/stable/linux-stable.git/commit/?h=linux-4.5.y&id=be19315585fa23cc
> > 9a2758e9f29f01b1095e134f
> 
> Yeah, looks like the relevant commit went into 4.3, so stable 4.4
> should get the fix as well. Cc:ing stable folks...

Now applied, thanks.

greg k-h

Re: "drm/i915: Update CDCLK_FREQ register on BDW after changing cdclk frequency" to 4.4.x as well?

[Greg KH]

On Sat, Jun 04, 2016 at 01:52:44PM -0700, Greg KH wrote:
> On Fri, May 27, 2016 at 07:34:39PM +0300, Ville Syrj�l� wrote:
> > On Fri, May 27, 2016 at 03:20:04PM +0000, Joakim Tjernlund wrote:
> > > I see that above patch is in 4.5 but not in 4.4, should it not be in 4.4 as well?
> > > 
> > > Link to commit in 4.5
> > > https://git.kernel.org/cgit/linux/kernel/git/stable/linux-stable.git/commit/?h=linux-4.5.y&id=be19315585fa23cc
> > > 9a2758e9f29f01b1095e134f
> > 
> > Yeah, looks like the relevant commit went into 4.3, so stable 4.4
> > should get the fix as well. Cc:ing stable folks...
> 
> Now applied, thanks.

Oops, no, it breaks the build, if it's needed there, can someone provide
a working backport?

thanks,

greg k-h

[PATCH stable-4.4] drm/i915: Update CDCLK_FREQ register on BDW after changing cdclk frequency

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

commit a04e23d42a1ce5d5f421692bb1c7e9352832819d upstream

Update CDCLK_FREQ on BDW after changing the cdclk frequency. Not sure
if this is a late addition to the spec, or if I simply overlooked this
step when writing the original code.

This is what Bspec has to say about CDCLK_FREQ:
"Program this field to the CD clock frequency minus one. This is used to
 generate a divided down clock for miscellaneous timers in display."

And the "Broadwell Sequences for Changing CD Clock Frequency" section
clarifies this further:
"For CD clock 337.5 MHz, program 337 decimal.
 For CD clock 450 MHz, program 449 decimal.
 For CD clock 540 MHz, program 539 decimal.
 For CD clock 675 MHz, program 674 decimal."

Cc: <stable@vger.kernel.org> # v4.4
Cc: Mika Kahola <mika.kahola@intel.com>
Fixes: b432e5cfd5e9 ("drm/i915: BDW clock change support")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1461689194-6079-2-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
(cherry picked from commit 7f1052a8fa38df635ab0dc0e6025b64ab9834824)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      | 2 ++
 drivers/gpu/drm/i915/intel_display.c | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7e461dca564c..9ed9f6dde86f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7357,6 +7357,8 @@ enum skl_disp_power_wells {
 #define  TRANS_CLK_SEL_DISABLED		(0x0<<29)
 #define  TRANS_CLK_SEL_PORT(x)		(((x)+1)<<29)
 
+#define CDCLK_FREQ			0x46200
+
 #define TRANSA_MSA_MISC			0x60410
 #define TRANSB_MSA_MISC			0x61410
 #define TRANSC_MSA_MISC			0x62410
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index afa81691163d..5ed9881785ef 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9669,6 +9669,8 @@ static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
 	sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
 	mutex_unlock(&dev_priv->rps.hw_lock);
 
+	I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
+
 	intel_update_cdclk(dev);
 
 	WARN(cdclk != dev_priv->cdclk_freq,
-- 
2.7.4