* [PATCH] irqchip/gic: Allow self-SGIs for SMP on UP configurations
@ 2016-09-09 13:42 Fabio Estevam
2016-09-09 13:53 ` Greg KH
0 siblings, 1 reply; 3+ messages in thread
From: Fabio Estevam @ 2016-09-09 13:42 UTC (permalink / raw)
To: stable; +Cc: marc.zyngier, Fabio Estevam
From: Marc Zyngier <marc.zyngier@arm.com>
On systems where a single CPU is present, the GIC may not support
having SGIs delivered to a target list. In that case, we use the
self-SGI mechanism to allow the interrupt to be delivered locally.
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
---
drivers/irqchip/irq-gic.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index c2cab57..390fac5 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -769,6 +769,13 @@ static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
int cpu;
unsigned long flags, map = 0;
+ if (unlikely(nr_cpu_ids == 1)) {
+ /* Only one CPU? let's do a self-IPI... */
+ writel_relaxed(2 << 24 | irq,
+ gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
+ return;
+ }
+
raw_spin_lock_irqsave(&irq_controller_lock, flags);
/* Convert our logical CPU mask into a physical one. */
--
1.9.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] irqchip/gic: Allow self-SGIs for SMP on UP configurations
2016-09-09 13:42 [PATCH] irqchip/gic: Allow self-SGIs for SMP on UP configurations Fabio Estevam
@ 2016-09-09 13:53 ` Greg KH
2016-09-09 13:56 ` Fabio Estevam
0 siblings, 1 reply; 3+ messages in thread
From: Greg KH @ 2016-09-09 13:53 UTC (permalink / raw)
To: Fabio Estevam; +Cc: stable, marc.zyngier, Fabio Estevam
On Fri, Sep 09, 2016 at 10:42:37AM -0300, Fabio Estevam wrote:
> From: Marc Zyngier <marc.zyngier@arm.com>
>
> On systems where a single CPU is present, the GIC may not support
> having SGIs delivered to a target list. In that case, we use the
> self-SGI mechanism to allow the interrupt to be delivered locally.
>
> Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
> ---
> drivers/irqchip/irq-gic.c | 7 +++++++
> 1 file changed, 7 insertions(+)
<formletter>
This is not the correct way to submit patches for inclusion in the
stable kernel tree. Please read Documentation/stable_kernel_rules.txt
for how to do this properly.
</formletter>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] irqchip/gic: Allow self-SGIs for SMP on UP configurations
2016-09-09 13:53 ` Greg KH
@ 2016-09-09 13:56 ` Fabio Estevam
0 siblings, 0 replies; 3+ messages in thread
From: Fabio Estevam @ 2016-09-09 13:56 UTC (permalink / raw)
To: Greg KH; +Cc: stable, Marc Zyngier, Fabio Estevam
Hi Greg,
On Fri, Sep 9, 2016 at 10:53 AM, Greg KH <greg@kroah.com> wrote:
> This is not the correct way to submit patches for inclusion in the
> stable kernel tree. Please read Documentation/stable_kernel_rules.txt
> for how to do this properly.
Yes, I have fixed it in v2, thanks.
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2016-09-09 13:56 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2016-09-09 13:42 [PATCH] irqchip/gic: Allow self-SGIs for SMP on UP configurations Fabio Estevam
2016-09-09 13:53 ` Greg KH
2016-09-09 13:56 ` Fabio Estevam
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).