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From: Greg KH <gregkh@linuxfoundation.org>
To: Lyude <lyude@redhat.com>
Cc: stable@vger.kernel.org, Hans de Goede <hdegoede@redhat.com>,
	Daniel Vetter <daniel.vetter@intel.com>,
	Jani Nikula <jani.nikula@linux.intel.com>,
	David Airlie <airlied@linux.ie>,
	intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH 0/5] drm/i915/skl: Backport watermark fixes for 4.8.y
Date: Fri, 28 Oct 2016 09:47:29 -0400	[thread overview]
Message-ID: <20161028134729.GA18568@kroah.com> (raw)
In-Reply-To: <1477510599-14843-1-git-send-email-lyude@redhat.com>

On Wed, Oct 26, 2016 at 03:36:32PM -0400, Lyude wrote:
> Now that these have finally made it into 4.9, it's time to finally backport
> these fixes. Skylake has been a mess in multi-monitor setups for a while now
> because up until recently we've been updating the watermarks on Skylake just
> like we would for previous generations of Intel GPUs. This means updating
> attributes for each plane, and then only after they've been updated writing
> their new watermark values.
> 
> The problem with this approach is Skylake has double buffered watermark
> registers that are flipped at the same time as the rest of the plane registers.
> This means that the original approach will leave planes active with new
> attributes but without the required watermark programming that would ensure the
> display pipe reads enough data from each plane. As a result, pipes start to
> underrun and the user's displays starts to flicker heavily. Usually in response
> to plugging in new monitors, or moving cursors from one screen to another
> (which triggers a plane and watermark update).
> 
> Additionally, issues were found with the original code for configuring ddb,
> display data buffer, allocations between display planes on Skylake. On Skylake
> all planes have space allocated to them in the ddb, and the hardware requires
> that these allocations never overlap at any point in time. Because ddb
> allocations were not updated alongside plane attributes despite also being
> double buffered registers armed by plane updates, planes were likely to get
> stuck momentarily with ddb allocations that overlapped one another. This would
> also lead to pipe underruns and display flickering.
> 
> The new approach fixes this problem by making sure that on Skylake, attributes
> for display planes are always updated at the same time as the watermarks, and
> pipes are updated in an order that ensures their ddb allocations don't
> overlap at any point between plane updates. This ensures the display pipes are
> always programmed correctly, and dramatically reduces the chance of display
> flickering.
> 
> (note: my e-mail has changed since these patches were upstreamed, and I updated
> the e-mails in these patches to reflect this. if this is wrong I will be happy
> to update and resend the patches).

Thanks for these, all now queued up.

greg k-h

      parent reply	other threads:[~2016-10-28 13:47 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-10-26 19:36 [PATCH 0/5] drm/i915/skl: Backport watermark fixes for 4.8.y Lyude
2016-10-26 19:36 ` [PATCH 1/5] drm/i915/skl: Update plane watermarks atomically during plane updates Lyude
2016-10-26 19:36 ` [PATCH 2/5] drm/i915: Move CRTC updating in atomic_commit into it's own hook Lyude
2016-10-26 19:36 ` [PATCH 3/5] drm/i915/skl: Update DDB values atomically with wms/plane attrs Lyude
2016-10-26 19:36 ` [PATCH 4/5] drm/i915/skl: Don't try to update plane watermarks if they haven't changed Lyude
2016-10-26 19:36 ` [PATCH 5/5] drm/i915/gen9: only add the planes actually affected by ddb changes Lyude
2016-10-27  6:24 ` [Intel-gfx] [PATCH 0/5] drm/i915/skl: Backport watermark fixes for 4.8.y Daniel Vetter
2016-10-28 13:47 ` Greg KH [this message]

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