From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtp.codeaurora.org ([198.145.29.96]:58722 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753461AbcKBA14 (ORCPT ); Tue, 1 Nov 2016 20:27:56 -0400 Date: Tue, 1 Nov 2016 17:27:54 -0700 From: Stephen Boyd To: Scott Wood Cc: Michael Turquette , linux-clk@vger.kernel.org, Shawn Guo , linux-arm-kernel@lists.infradead.org, stable@vger.kernel.org Subject: Re: [PATCH] clk: qoriq: Don't allow CPU clocks higher than starting value Message-ID: <20161102002754.GF16026@codeaurora.org> References: <1476729743-15563-1-git-send-email-oss@buserror.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1476729743-15563-1-git-send-email-oss@buserror.net> Sender: stable-owner@vger.kernel.org List-ID: On 10/17, Scott Wood wrote: > The boot-time frequency of a CPU is considered its rated maximum, as we > have no other source of such information. However, this was previously > only used for chips with 80% restrictions on secondary PLLs. This > usually wasn't a problem because most chips/configs boot with a divider > of /1, with other dividers being used only for dynamic frequency > reduction. However, at least one config (LS1021A at less than 1 GHz) > uses a different divider for top speed. This was causing cpufreq to set > a frequency beyond the chip's rated speed. > > This is fixed by applying a 100%-of-initial-speed limit to all CPU PLLs, > similar to the existing 80% limit that only applied to some. > > Signed-off-by: Scott Wood > Cc: stable@vger.kernel.org > --- All silence, so I applied to clk-fixes because presumably this is some sort of badness we need to fix quickly. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project