From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga06.intel.com ([134.134.136.31]:65386 "EHLO mga06.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756039AbcK2Tjd (ORCPT ); Tue, 29 Nov 2016 14:39:33 -0500 Date: Tue, 29 Nov 2016 21:36:23 +0200 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Matthew Auld Cc: Intel Graphics Development , Matthew Auld , stable@vger.kernel.org Subject: Re: [Intel-gfx] [PATCH] drm/i915: Initialize dev_priv->atomic_cdclk_freq at init time Message-ID: <20161129193623.GV31595@intel.com> References: <1480428837-4207-1-git-send-email-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Sender: stable-owner@vger.kernel.org List-ID: On Tue, Nov 29, 2016 at 02:40:45PM +0000, Matthew Auld wrote: > On 29 November 2016 at 14:13, wrote: > > From: Ville Syrj�l� > > > > Looks like we're only initializing dev_priv->atomic_cdclk_freq > > at resume and commit times, not at init time. Let's do that as > > well. > > > > We're now hitting the 'WARN_ON(intel_state->cdclk == 0)' in > > hsw_compute_linetime_wm() on account of populating > > intel_state->cdclk from dev_priv->atomic_cdclk_freq. > > Previously we were mispopulating intel_state->cdclk with > > dev_priv->cdclk_freq which always had a proper value at init > > time and hence the WARN_ON() didn't trigger. > > > > Cc: stable@vger.kernel.org > > Cc: Matthew Auld > > Reported-by: Matthew Auld > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98902 > > Fixes: e0ca7a6be38c ("drm/i915: Fix cdclk vs. dev_cdclk mess when not recomputing things") > > Signed-off-by: Ville Syrj�l� > Tested-by: Matthew Auld > Reviewed-by: Matthew Auld Pushed to dinq. Thanks for the testing and review. -- Ville Syrj�l� Intel OTC