From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtp.codeaurora.org ([198.145.29.96]:54480 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752785AbcLHWzO (ORCPT ); Thu, 8 Dec 2016 17:55:14 -0500 Date: Thu, 8 Dec 2016 14:55:12 -0800 From: Stephen Boyd To: Boris Brezillon Cc: Mike Turquette , linux-clk@vger.kernel.org, Florian Fainelli , Ray Jui , Scott Branden , bcm-kernel-feedback-list@broadcom.com, Stephen Warren , Lee Jones , Eric Anholt , linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, stable@vger.kernel.org Subject: Re: [PATCH] clk: bcm2835: Avoid overwriting the div info when disabling a pll_div clk Message-ID: <20161208225512.GR5423@codeaurora.org> References: <1480620441-5442-1-git-send-email-boris.brezillon@free-electrons.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1480620441-5442-1-git-send-email-boris.brezillon@free-electrons.com> Sender: stable-owner@vger.kernel.org List-ID: On 12/01, Boris Brezillon wrote: > bcm2835_pll_divider_off() is resetting the divider field in the A2W reg > to zero when disabling the clock. > > Make sure we preserve this value by reading the previous a2w_reg value > first and ORing the result with A2W_PLL_CHANNEL_DISABLE. > > Signed-off-by: Boris Brezillon > Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain clocks") > Cc: > --- Applied to clk-next -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project