Re: FAILED: patch "[PATCH] perf/x86: Fix full width counter, counter overflow" failed to apply to 4.4-stable tree

[Greg KH <gregkh@linuxfoundation.org>]

Nevermind, I got it to work, sorry for the noise...

greg k-h

On Mon, Dec 12, 2016 at 02:37:22PM -0800, gregkh@linuxfoundation.org wrote:
> 
> The patch below does not apply to the 4.4-stable tree.
> If someone wants it applied there, or to any other stable or longterm
> tree, then please email the backport, including the original git commit
> id to <stable@vger.kernel.org>.
> 
> thanks,
> 
> greg k-h
> 
> ------------------ original commit in Linus's tree ------------------
> 
> >From 7f612a7f0bc13a2361a152862435b7941156b6af Mon Sep 17 00:00:00 2001
> From: "Peter Zijlstra (Intel)" <peterz@infradead.org>
> Date: Tue, 29 Nov 2016 20:33:28 +0000
> Subject: [PATCH] perf/x86: Fix full width counter, counter overflow
> 
> Lukasz reported that perf stat counters overflow handling is broken on KNL/SLM.
> 
> Both these parts have full_width_write set, and that does indeed have
> a problem. In order to deal with counter wrap, we must sample the
> counter at at least half the counter period (see also the sampling
> theorem) such that we can unambiguously reconstruct the count.
> 
> However commit:
> 
>   069e0c3c4058 ("perf/x86/intel: Support full width counting")
> 
> sets the sampling interval to the full period, not half.
> 
> Fixing that exposes another issue, in that we must not sign extend the
> delta value when we shift it right; the counter cannot have
> decremented after all.
> 
> With both these issues fixed, counter overflow functions correctly
> again.
> 
> Reported-by: Lukasz Odzioba <lukasz.odzioba@intel.com>
> Tested-by: Liang, Kan <kan.liang@intel.com>
> Tested-by: Odzioba, Lukasz <lukasz.odzioba@intel.com>
> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
> Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
> Cc: Jiri Olsa <jolsa@redhat.com>
> Cc: Linus Torvalds <torvalds@linux-foundation.org>
> Cc: Peter Zijlstra <peterz@infradead.org>
> Cc: Stephane Eranian <eranian@google.com>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: Vince Weaver <vincent.weaver@maine.edu>
> Cc: stable@vger.kernel.org
> Fixes: 069e0c3c4058 ("perf/x86/intel: Support full width counting")
> Signed-off-by: Ingo Molnar <mingo@kernel.org>
> 
> diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
> index 9d4bf3ab049e..6e395c996900 100644
> --- a/arch/x86/events/core.c
> +++ b/arch/x86/events/core.c
> @@ -69,7 +69,7 @@ u64 x86_perf_event_update(struct perf_event *event)
>  	int shift = 64 - x86_pmu.cntval_bits;
>  	u64 prev_raw_count, new_raw_count;
>  	int idx = hwc->idx;
> -	s64 delta;
> +	u64 delta;
>  
>  	if (idx == INTEL_PMC_IDX_FIXED_BTS)
>  		return 0;
> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> index a74a2dbc0180..cb8522290e6a 100644
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
> @@ -4034,7 +4034,7 @@ __init int intel_pmu_init(void)
>  
>  	/* Support full width counters using alternative MSR range */
>  	if (x86_pmu.intel_cap.full_width_write) {
> -		x86_pmu.max_period = x86_pmu.cntval_mask;
> +		x86_pmu.max_period = x86_pmu.cntval_mask >> 1;
>  		x86_pmu.perfctr = MSR_IA32_PMC0;
>  		pr_cont("full-width counters, ");
>  	}
> 
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