From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.free-electrons.com ([62.4.15.54]:38259 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751393AbdEJHS3 (ORCPT ); Wed, 10 May 2017 03:18:29 -0400 Date: Wed, 10 May 2017 09:18:17 +0200 From: Thomas Petazzoni To: Giuseppe CAVALLARO Cc: Corentin Labbe , Alexandre Torgue , , Subject: Re: [PATCH] net: ethernet: stmmac: properly set PS bit in MII configurations during reset Message-ID: <20170510091817.58f4e843@free-electrons.com> In-Reply-To: References: <1493286329-24448-1-git-send-email-thomas.petazzoni@free-electrons.com> <20170503143032.GA22106@Red> <49297ed2-84dc-3e9b-8f40-af915476a091@st.com> <20170508211230.58aeead9@free-electrons.com> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: stable-owner@vger.kernel.org List-ID: Hello, On Wed, 10 May 2017 09:03:12 +0200, Giuseppe CAVALLARO wrote: > > Please, read again my patch and the description of the problem that I > > have sent. But basically, any solution that does not allow to set the > > PS bit between asserting the DMA reset bit and polling for it to clear > > will not work for MII PHYs. > > yes your point was clear to me, I was just wondering if we could find an > easier way > to solve it w/o changing the API, adding the set_ps and propagating the > "interface" > inside the DMA reset. > > Maybe this could be fixed in the glue-logic in some way. Let me know > what do you think. Well, it's more up to you to tell me how you would like this be solved. We figured out what the problem was, but I don't know well enough the architecture of the driver to decide how the solution to this problem should be designed. I made an initial simple proposal to show what is needed, but I'm definitely open to suggestions. Best regards, Thomas -- Thomas Petazzoni, CTO, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com