* [PATCH 4.4.y] drm: rcar-du: lvds: Fix PLL frequency-related configuration
@ 2017-08-16 8:53 Nhan Nguyen
2017-08-16 8:53 ` [PATCH 4.4.y] drm: rcar-du: lvds: Rename PLLEN bit to PLLON Nhan Nguyen
` (3 more replies)
0 siblings, 4 replies; 8+ messages in thread
From: Nhan Nguyen @ 2017-08-16 8:53 UTC (permalink / raw)
To: greg; +Cc: Laurent Pinchart, stable, Thong Ho, Nhan Nguyen
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
commit 5e1ac3bdc6bbb4f378251b87625b8acfbfc4ae82 upstream.
The frequency checks don't match the datasheet, fix them.
Cc: stable@vger.kernel.org
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Thong Ho <thong.ho.px@rvc.renesas.com>
Signed-off-by: Nhan Nguyen <nhan.nguyen.yb@renesas.com>
---
drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c b/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c
index 85043c5..5188972 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c
@@ -56,11 +56,11 @@ static int rcar_du_lvdsenc_start(struct rcar_du_lvdsenc *lvds,
return ret;
/* PLL clock configuration */
- if (freq <= 38000)
+ if (freq < 39000)
pllcr = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_38M;
- else if (freq <= 60000)
+ else if (freq < 61000)
pllcr = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_60M;
- else if (freq <= 121000)
+ else if (freq < 121000)
pllcr = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_121M;
else
pllcr = LVDPLLCR_PLLDLYCNT_150M;
--
1.9.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 4.4.y] drm: rcar-du: lvds: Rename PLLEN bit to PLLON
2017-08-16 8:53 [PATCH 4.4.y] drm: rcar-du: lvds: Fix PLL frequency-related configuration Nhan Nguyen
@ 2017-08-16 8:53 ` Nhan Nguyen
2017-08-16 8:53 ` [PATCH 4.4.y] drm: rcar-du: Fix crash in encoder failure error path Nhan Nguyen
` (2 subsequent siblings)
3 siblings, 0 replies; 8+ messages in thread
From: Nhan Nguyen @ 2017-08-16 8:53 UTC (permalink / raw)
To: greg; +Cc: Laurent Pinchart, stable, Thong Ho, Nhan Nguyen
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
commit 82e7c5e4964545352accff4b44bbcaa2c38e7fc1 upstream.
The bit is named PLLON in the datasheet, rename it.
Cc: stable@vger.kernel.org
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Thong Ho <thong.ho.px@rvc.renesas.com>
Signed-off-by: Nhan Nguyen <nhan.nguyen.yb@renesas.com>
---
drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c | 2 +-
drivers/gpu/drm/rcar-du/rcar_lvds_regs.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c b/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c
index 5188972..873e04a 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c
@@ -102,7 +102,7 @@ static int rcar_du_lvdsenc_start(struct rcar_du_lvdsenc *lvds,
/* Turn the PLL on, wait for the startup delay, and turn the output
* on.
*/
- lvdcr0 |= LVDCR0_PLLEN;
+ lvdcr0 |= LVDCR0_PLLON;
rcar_lvds_write(lvds, LVDCR0, lvdcr0);
usleep_range(100, 150);
diff --git a/drivers/gpu/drm/rcar-du/rcar_lvds_regs.h b/drivers/gpu/drm/rcar-du/rcar_lvds_regs.h
index 77cf928..b1eafd0 100644
--- a/drivers/gpu/drm/rcar-du/rcar_lvds_regs.h
+++ b/drivers/gpu/drm/rcar-du/rcar_lvds_regs.h
@@ -18,7 +18,7 @@
#define LVDCR0_DMD (1 << 12)
#define LVDCR0_LVMD_MASK (0xf << 8)
#define LVDCR0_LVMD_SHIFT 8
-#define LVDCR0_PLLEN (1 << 4)
+#define LVDCR0_PLLON (1 << 4)
#define LVDCR0_BEN (1 << 2)
#define LVDCR0_LVEN (1 << 1)
#define LVDCR0_LVRES (1 << 0)
--
1.9.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 4.4.y] drm: rcar-du: Fix crash in encoder failure error path
2017-08-16 8:53 [PATCH 4.4.y] drm: rcar-du: lvds: Fix PLL frequency-related configuration Nhan Nguyen
2017-08-16 8:53 ` [PATCH 4.4.y] drm: rcar-du: lvds: Rename PLLEN bit to PLLON Nhan Nguyen
@ 2017-08-16 8:53 ` Nhan Nguyen
2017-08-27 12:21 ` Greg KH
2017-08-16 8:53 ` [PATCH 4.4.y] drm: rcar-du: Fix display timing controller parameter Nhan Nguyen
2017-08-16 8:53 ` [PATCH 4.4.y] drm: rcar-du: Fix H/V sync signal polarity configuration Nhan Nguyen
3 siblings, 1 reply; 8+ messages in thread
From: Nhan Nguyen @ 2017-08-16 8:53 UTC (permalink / raw)
To: greg; +Cc: Laurent Pinchart, stable, Thong Ho, Nhan Nguyen
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
commit 05ee29e94acf0d4b3998c3f93374952de8f90176 upstream.
When an encoder fails to initialize the driver prints an error message
to the kernel log. The message contains the name of the encoder's DT
node, which is NULL for internal encoders. Use the of_node_full_name()
macro to avoid dereferencing a NULL pointer, print the output number to
add more context to the error, and make sure we still own a reference to
the encoder's DT node by delaying the of_node_put() call.
Cc: stable@vger.kernel.org
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
Signed-off-by: Thong Ho <thong.ho.px@rvc.renesas.com>
Signed-off-by: Nhan Nguyen <nhan.nguyen.yb@renesas.com>
---
drivers/gpu/drm/rcar-du/rcar_du_kms.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
index ca12e8c..3e3d036 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
@@ -642,13 +642,13 @@ static int rcar_du_encoders_init_one(struct rcar_du_device *rcdu,
}
ret = rcar_du_encoder_init(rcdu, enc_type, output, encoder, connector);
- of_node_put(encoder);
- of_node_put(connector);
-
if (ret && ret != -EPROBE_DEFER)
dev_warn(rcdu->dev,
- "failed to initialize encoder %s (%d), skipping\n",
- encoder->full_name, ret);
+ "failed to initialize encoder %s on output %u (%d), skipping\n",
+ of_node_full_name(encoder), output, ret);
+
+ of_node_put(encoder);
+ of_node_put(connector);
return ret;
}
--
1.9.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 4.4.y] drm: rcar-du: Fix display timing controller parameter
2017-08-16 8:53 [PATCH 4.4.y] drm: rcar-du: lvds: Fix PLL frequency-related configuration Nhan Nguyen
2017-08-16 8:53 ` [PATCH 4.4.y] drm: rcar-du: lvds: Rename PLLEN bit to PLLON Nhan Nguyen
2017-08-16 8:53 ` [PATCH 4.4.y] drm: rcar-du: Fix crash in encoder failure error path Nhan Nguyen
@ 2017-08-16 8:53 ` Nhan Nguyen
2017-08-27 12:22 ` Greg KH
2017-08-16 8:53 ` [PATCH 4.4.y] drm: rcar-du: Fix H/V sync signal polarity configuration Nhan Nguyen
3 siblings, 1 reply; 8+ messages in thread
From: Nhan Nguyen @ 2017-08-16 8:53 UTC (permalink / raw)
To: greg; +Cc: Koji Matsuoka, stable, Laurent Pinchart, Thong Ho, Nhan Nguyen
From: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
commit 9cdced8a39c04cf798ddb2a27cb5952f7d39f633 upstream.
There is a bug in the setting of the DES (Display Enable Signal)
register. This current setting occurs 1 dot left shift. The DES
register should be set minus one value about the specifying value
with H/W specification. This patch corrects it.
Cc: stable@vger.kernel.org
Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Thong Ho <thong.ho.px@rvc.renesas.com>
Signed-off-by: Nhan Nguyen <nhan.nguyen.yb@renesas.com>
---
drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
index 9255b9c..c6b279d 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
@@ -171,7 +171,7 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
mode->crtc_vsync_start - 1);
rcar_du_crtc_write(rcrtc, VCR, mode->crtc_vtotal - 1);
- rcar_du_crtc_write(rcrtc, DESR, mode->htotal - mode->hsync_start);
+ rcar_du_crtc_write(rcrtc, DESR, mode->htotal - mode->hsync_start - 1);
rcar_du_crtc_write(rcrtc, DEWR, mode->hdisplay);
}
--
1.9.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 4.4.y] drm: rcar-du: Fix H/V sync signal polarity configuration
2017-08-16 8:53 [PATCH 4.4.y] drm: rcar-du: lvds: Fix PLL frequency-related configuration Nhan Nguyen
` (2 preceding siblings ...)
2017-08-16 8:53 ` [PATCH 4.4.y] drm: rcar-du: Fix display timing controller parameter Nhan Nguyen
@ 2017-08-16 8:53 ` Nhan Nguyen
2017-08-27 12:23 ` Greg KH
3 siblings, 1 reply; 8+ messages in thread
From: Nhan Nguyen @ 2017-08-16 8:53 UTC (permalink / raw)
To: greg; +Cc: Koji Matsuoka, stable, Laurent Pinchart, Thong Ho, Nhan Nguyen
From: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
commit fd1adef3bff0663c5ac31b45bc4a05fafd43d19b upstream.
The VSL and HSL bits in the DSMR register set the corresponding
horizontal and vertical sync signal polarity to active high. The code
got it the wrong way around, fix it.
Cc: stable@vger.kernel.org
Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Thong Ho <thong.ho.px@rvc.renesas.com>
Signed-off-by: Nhan Nguyen <nhan.nguyen.yb@renesas.com>
---
drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
index c6b279d..9befd62 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
@@ -148,8 +148,8 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? OTAR2 : OTAR, 0);
/* Signal polarities */
- value = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? 0 : DSMR_VSL)
- | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? 0 : DSMR_HSL)
+ value = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? DSMR_VSL : 0)
+ | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? DSMR_HSL : 0)
| DSMR_DIPM_DE | DSMR_CSPM;
rcar_du_crtc_write(rcrtc, DSMR, value);
--
1.9.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 4.4.y] drm: rcar-du: Fix crash in encoder failure error path
2017-08-16 8:53 ` [PATCH 4.4.y] drm: rcar-du: Fix crash in encoder failure error path Nhan Nguyen
@ 2017-08-27 12:21 ` Greg KH
0 siblings, 0 replies; 8+ messages in thread
From: Greg KH @ 2017-08-27 12:21 UTC (permalink / raw)
To: Nhan Nguyen; +Cc: Laurent Pinchart, stable, Thong Ho
On Wed, Aug 16, 2017 at 03:53:48PM +0700, Nhan Nguyen wrote:
> From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
>
> commit 05ee29e94acf0d4b3998c3f93374952de8f90176 upstream.
>
> When an encoder fails to initialize the driver prints an error message
> to the kernel log. The message contains the name of the encoder's DT
> node, which is NULL for internal encoders. Use the of_node_full_name()
> macro to avoid dereferencing a NULL pointer, print the output number to
> add more context to the error, and make sure we still own a reference to
> the encoder's DT node by delaying the of_node_put() call.
>
> Cc: stable@vger.kernel.org
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Reviewed-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
> Signed-off-by: Thong Ho <thong.ho.px@rvc.renesas.com>
> Signed-off-by: Nhan Nguyen <nhan.nguyen.yb@renesas.com>
> ---
> drivers/gpu/drm/rcar-du/rcar_du_kms.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
I also added this to 4.9-stable.
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 4.4.y] drm: rcar-du: Fix display timing controller parameter
2017-08-16 8:53 ` [PATCH 4.4.y] drm: rcar-du: Fix display timing controller parameter Nhan Nguyen
@ 2017-08-27 12:22 ` Greg KH
0 siblings, 0 replies; 8+ messages in thread
From: Greg KH @ 2017-08-27 12:22 UTC (permalink / raw)
To: Nhan Nguyen; +Cc: Koji Matsuoka, stable, Laurent Pinchart, Thong Ho
On Wed, Aug 16, 2017 at 03:53:49PM +0700, Nhan Nguyen wrote:
> From: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
>
> commit 9cdced8a39c04cf798ddb2a27cb5952f7d39f633 upstream.
>
> There is a bug in the setting of the DES (Display Enable Signal)
> register. This current setting occurs 1 dot left shift. The DES
> register should be set minus one value about the specifying value
> with H/W specification. This patch corrects it.
>
> Cc: stable@vger.kernel.org
> Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Thong Ho <thong.ho.px@rvc.renesas.com>
> Signed-off-by: Nhan Nguyen <nhan.nguyen.yb@renesas.com>
> ---
> drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Also added to 4.9-stable
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 4.4.y] drm: rcar-du: Fix H/V sync signal polarity configuration
2017-08-16 8:53 ` [PATCH 4.4.y] drm: rcar-du: Fix H/V sync signal polarity configuration Nhan Nguyen
@ 2017-08-27 12:23 ` Greg KH
0 siblings, 0 replies; 8+ messages in thread
From: Greg KH @ 2017-08-27 12:23 UTC (permalink / raw)
To: Nhan Nguyen; +Cc: Koji Matsuoka, stable, Laurent Pinchart, Thong Ho
On Wed, Aug 16, 2017 at 03:53:50PM +0700, Nhan Nguyen wrote:
> From: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
>
> commit fd1adef3bff0663c5ac31b45bc4a05fafd43d19b upstream.
>
> The VSL and HSL bits in the DSMR register set the corresponding
> horizontal and vertical sync signal polarity to active high. The code
> got it the wrong way around, fix it.
>
> Cc: stable@vger.kernel.org
> Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Thong Ho <thong.ho.px@rvc.renesas.com>
> Signed-off-by: Nhan Nguyen <nhan.nguyen.yb@renesas.com>
> ---
> drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Also added to 4.9-stable
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2017-08-27 12:23 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2017-08-16 8:53 [PATCH 4.4.y] drm: rcar-du: lvds: Fix PLL frequency-related configuration Nhan Nguyen
2017-08-16 8:53 ` [PATCH 4.4.y] drm: rcar-du: lvds: Rename PLLEN bit to PLLON Nhan Nguyen
2017-08-16 8:53 ` [PATCH 4.4.y] drm: rcar-du: Fix crash in encoder failure error path Nhan Nguyen
2017-08-27 12:21 ` Greg KH
2017-08-16 8:53 ` [PATCH 4.4.y] drm: rcar-du: Fix display timing controller parameter Nhan Nguyen
2017-08-27 12:22 ` Greg KH
2017-08-16 8:53 ` [PATCH 4.4.y] drm: rcar-du: Fix H/V sync signal polarity configuration Nhan Nguyen
2017-08-27 12:23 ` Greg KH
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