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Date: Sun, 27 Aug 2017 14:22:19 +0200
From: Greg KH <greg@kroah.com>
To: Nhan Nguyen <nhan.nguyen.yb@renesas.com>
Cc: Koji Matsuoka <koji.matsuoka.xm@renesas.com>,
        stable@vger.kernel.org,
        Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>,
        Thong Ho <thong.ho.px@rvc.renesas.com>
Subject: Re: [PATCH 4.4.y] drm: rcar-du: Fix display timing controller
 parameter
Message-ID: <20170827122219.GB2963@kroah.com>
References: <20170816085350.3180-1-nhan.nguyen.yb@renesas.com>
 <20170816085350.3180-4-nhan.nguyen.yb@renesas.com>
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On Wed, Aug 16, 2017 at 03:53:49PM +0700, Nhan Nguyen wrote:
> From: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
> 
> commit 9cdced8a39c04cf798ddb2a27cb5952f7d39f633 upstream.
> 
> There is a bug in the setting of the DES (Display Enable Signal)
> register. This current setting occurs 1 dot left shift. The DES
> register should be set minus one value about the specifying value
> with H/W specification. This patch corrects it.
> 
> Cc: stable@vger.kernel.org
> Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Thong Ho <thong.ho.px@rvc.renesas.com>
> Signed-off-by: Nhan Nguyen <nhan.nguyen.yb@renesas.com>
> ---
>  drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Also added to 4.9-stable