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Date: Sun, 27 Aug 2017 14:23:17 +0200
From: Greg KH <greg@kroah.com>
To: Nhan Nguyen <nhan.nguyen.yb@renesas.com>
Cc: Koji Matsuoka <koji.matsuoka.xm@renesas.com>,
        stable@vger.kernel.org,
        Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>,
        Thong Ho <thong.ho.px@rvc.renesas.com>
Subject: Re: [PATCH 4.4.y] drm: rcar-du: Fix H/V sync signal polarity
 configuration
Message-ID: <20170827122317.GC2963@kroah.com>
References: <20170816085350.3180-1-nhan.nguyen.yb@renesas.com>
 <20170816085350.3180-5-nhan.nguyen.yb@renesas.com>
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On Wed, Aug 16, 2017 at 03:53:50PM +0700, Nhan Nguyen wrote:
> From: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
> 
> commit fd1adef3bff0663c5ac31b45bc4a05fafd43d19b upstream.
> 
> The VSL and HSL bits in the DSMR register set the corresponding
> horizontal and vertical sync signal polarity to active high. The code
> got it the wrong way around, fix it.
> 
> Cc: stable@vger.kernel.org
> Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Thong Ho <thong.ho.px@rvc.renesas.com>
> Signed-off-by: Nhan Nguyen <nhan.nguyen.yb@renesas.com>
> ---
>  drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)

Also added to 4.9-stable