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Date: Fri, 24 Nov 2017 14:55:28 +0200
From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org, stable@vger.kernel.org,
        Daniel Kurtz <djkurtz@chromium.org>,
        Daniel Vetter <daniel.vetter@ffwll.ch>,
        Sean Paul <seanpaul@chromium.org>
Subject: Re: [PATCH 1/3] drm/i915: Pass the correct msgs to
 gmbus_is_index_read()
Message-ID: <20171124125528.GC10981@intel.com>
References: <20171123194157.25367-1-ville.syrjala@linux.intel.com>
 <151147024152.28677.8625638122230579027@mail.alporthouse.com>
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On Thu, Nov 23, 2017 at 08:50:41PM +0000, Chris Wilson wrote:
> Quoting Ville Syrjala (2017-11-23 19:41:55)
> > From: Ville Syrj�l� <ville.syrjala@linux.intel.com>
> > 
> > We're supposed to examine msgs[i] and msgs[i+1] to see if they
> > form a pair suitable for an indexed transfer. But in reality
> > we're examining msgs[0] and msgs[1]. Fix this.
> > 
> > Cc: stable@vger.kernel.org
> > Cc: Daniel Kurtz <djkurtz@chromium.org>
> > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> > Cc: Sean Paul <seanpaul@chromium.org>
> > Fixes: 56f9eac05489 ("drm/i915/intel_i2c: use INDEX cycles for i2c read transactions")
> > Signed-off-by: Ville Syrj�l� <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_i2c.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
> > index eb5827110d8f..165375cbef2f 100644
> > --- a/drivers/gpu/drm/i915/intel_i2c.c
> > +++ b/drivers/gpu/drm/i915/intel_i2c.c
> > @@ -484,7 +484,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
> >  
> >         for (; i < num; i += inc) {
> >                 inc = 1;
> > -               if (gmbus_is_index_read(msgs, i, num)) {
> > +               if (gmbus_is_index_read(&msgs[i], i, num)) {
> 
> i is passed to gmbus_is_index_read() and used as an index into msgs. So
> this should be accounted for right?

Doh. Yep, this patch is nonsense.

-- 
Ville Syrj�l�
Intel OTC