From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-f67.google.com ([74.125.82.67]:41715 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750853AbdLLRAC (ORCPT ); Tue, 12 Dec 2017 12:00:02 -0500 Received: by mail-wm0-f67.google.com with SMTP id g75so62031wme.0 for ; Tue, 12 Dec 2017 09:00:02 -0800 (PST) Date: Tue, 12 Dec 2017 17:59:56 +0100 From: Christoffer Dall To: stable@vger.kernel.org Cc: Marc Zyngier , gregkh@linuxfoundation.org, Kristina Martsenko Subject: Re: [PATCH v3.18 backport] arm64: KVM: fix VTTBR_BADDR_MASK BUG_ON off-by-one Message-ID: <20171212165956.GN910@cbox> References: <20171212125032.6292-1-christoffer.dall@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20171212125032.6292-1-christoffer.dall@linaro.org> Sender: stable-owner@vger.kernel.org List-ID: On Tue, Dec 12, 2017 at 01:50:31PM +0100, Christoffer Dall wrote: > From: Kristina Martsenko > > Commit 26aa7b3b1c0fb3f1a6176a0c1847204ef4355693 upstream. Please disregard this, I accidentally backported the arm64 patch instead of the arm patch. Another one (the correct one, hopefully) incoming, which backports 5553b142be11e794ebc0805950b2e8313f93d718 instead. Thanks (and sorry about the noise), -Christoffer > > VTTBR_BADDR_MASK is used to sanity check the size and alignment of the > VTTBR address. It seems to currently be off by one, thereby only > allowing up to 47-bit addresses (instead of 48-bit) and also > insufficiently checking the alignment. This patch fixes it. > > As an example, with 4k pages, before this patch we have: > > PHYS_MASK_SHIFT = 48 > VTTBR_X = 37 - 24 = 13 > VTTBR_BADDR_SHIFT = 13 - 1 = 12 > VTTBR_BADDR_MASK = ((1 << 35) - 1) << 12 = 0x00007ffffffff000 > > Which is wrong, because the mask doesn't allow bit 47 of the VTTBR > address to be set, and only requires the address to be 12-bit (4k) > aligned, while it actually needs to be 13-bit (8k) aligned because we > concatenate two 4k tables. > > With this patch, the mask becomes 0x0000ffffffffe000, which is what we > want. > > Fixes: 0369f6a34b9f ("arm64: KVM: EL2 register definitions") > Cc: # 3.11.x > Reviewed-by: Suzuki K Poulose > Reviewed-by: Christoffer Dall > Signed-off-by: Kristina Martsenko > Signed-off-by: Marc Zyngier > Signed-off-by: Christoffer Dall > --- > arch/arm64/include/asm/kvm_arm.h | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h > index 8afb863f5a9e..333ddd45dd1f 100644 > --- a/arch/arm64/include/asm/kvm_arm.h > +++ b/arch/arm64/include/asm/kvm_arm.h > @@ -160,8 +160,7 @@ > #define VTTBR_X (37 - VTCR_EL2_T0SZ_40B) > #endif > > -#define VTTBR_BADDR_SHIFT (VTTBR_X - 1) > -#define VTTBR_BADDR_MASK (((UL(1) << (PHYS_MASK_SHIFT - VTTBR_X)) - 1) << VTTBR_BADDR_SHIFT) > +#define VTTBR_BADDR_MASK (((UL(1) << (PHYS_MASK_SHIFT - VTTBR_X)) - 1) << VTTBR_X) > #define VTTBR_VMID_SHIFT (UL(48)) > #define VTTBR_VMID_MASK (UL(0xFF) << VTTBR_VMID_SHIFT) > > -- > 2.14.2 >