From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
To: linux-kernel@vger.kernel.org
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
stable@vger.kernel.org, Andrew Morton <akpm@linux-foundation.org>,
Andy Lutomirski <luto@amacapital.net>,
Andy Lutomirski <luto@kernel.org>, Borislav Petkov <bp@alien8.de>,
Brian Gerst <brgerst@gmail.com>,
Denys Vlasenko <dvlasenk@redhat.com>,
Josh Poimboeuf <jpoimboe@redhat.com>,
Linus Torvalds <torvalds@linux-foundation.org>,
Peter Zijlstra <peterz@infradead.org>,
Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@kernel.org>
Subject: [PATCH 4.14 059/159] x86/cpufeatures: Re-tabulate the X86_FEATURE definitions
Date: Fri, 22 Dec 2017 09:45:44 +0100 [thread overview]
Message-ID: <20171222084626.937271607@linuxfoundation.org> (raw)
In-Reply-To: <20171222084623.668990192@linuxfoundation.org>
4.14-stable review patch. If anyone has any objections, please let me know.
------------------
From: Ingo Molnar <mingo@kernel.org>
commit acbc845ffefd9fb70466182cd8555a26189462b2 upstream.
Over the years asm/cpufeatures.h has become somewhat of a mess: the original
tabulation style was too narrow, while x86 feature names also kept growing
in length, creating frequent field width overflows.
Re-tabulate it to make it wider and easier to read/modify. Also harmonize
the tabulation of the other defines in this file to match it.
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: Josh Poimboeuf <jpoimboe@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/20171031121723.28524-3-mingo@kernel.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
arch/x86/include/asm/cpufeatures.h | 512 ++++++++++++++++++-------------------
1 file changed, 256 insertions(+), 256 deletions(-)
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -13,8 +13,8 @@
/*
* Defines x86 CPU feature bits
*/
-#define NCAPINTS 18 /* N 32-bit words worth of info */
-#define NBUGINTS 1 /* N 32-bit bug flags */
+#define NCAPINTS 18 /* N 32-bit words worth of info */
+#define NBUGINTS 1 /* N 32-bit bug flags */
/*
* Note: If the comment begins with a quoted string, that string is used
@@ -28,163 +28,163 @@
*/
/* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */
-#define X86_FEATURE_FPU ( 0*32+ 0) /* Onboard FPU */
-#define X86_FEATURE_VME ( 0*32+ 1) /* Virtual Mode Extensions */
-#define X86_FEATURE_DE ( 0*32+ 2) /* Debugging Extensions */
-#define X86_FEATURE_PSE ( 0*32+ 3) /* Page Size Extensions */
-#define X86_FEATURE_TSC ( 0*32+ 4) /* Time Stamp Counter */
-#define X86_FEATURE_MSR ( 0*32+ 5) /* Model-Specific Registers */
-#define X86_FEATURE_PAE ( 0*32+ 6) /* Physical Address Extensions */
-#define X86_FEATURE_MCE ( 0*32+ 7) /* Machine Check Exception */
-#define X86_FEATURE_CX8 ( 0*32+ 8) /* CMPXCHG8 instruction */
-#define X86_FEATURE_APIC ( 0*32+ 9) /* Onboard APIC */
-#define X86_FEATURE_SEP ( 0*32+11) /* SYSENTER/SYSEXIT */
-#define X86_FEATURE_MTRR ( 0*32+12) /* Memory Type Range Registers */
-#define X86_FEATURE_PGE ( 0*32+13) /* Page Global Enable */
-#define X86_FEATURE_MCA ( 0*32+14) /* Machine Check Architecture */
-#define X86_FEATURE_CMOV ( 0*32+15) /* CMOV instructions */
+#define X86_FEATURE_FPU ( 0*32+ 0) /* Onboard FPU */
+#define X86_FEATURE_VME ( 0*32+ 1) /* Virtual Mode Extensions */
+#define X86_FEATURE_DE ( 0*32+ 2) /* Debugging Extensions */
+#define X86_FEATURE_PSE ( 0*32+ 3) /* Page Size Extensions */
+#define X86_FEATURE_TSC ( 0*32+ 4) /* Time Stamp Counter */
+#define X86_FEATURE_MSR ( 0*32+ 5) /* Model-Specific Registers */
+#define X86_FEATURE_PAE ( 0*32+ 6) /* Physical Address Extensions */
+#define X86_FEATURE_MCE ( 0*32+ 7) /* Machine Check Exception */
+#define X86_FEATURE_CX8 ( 0*32+ 8) /* CMPXCHG8 instruction */
+#define X86_FEATURE_APIC ( 0*32+ 9) /* Onboard APIC */
+#define X86_FEATURE_SEP ( 0*32+11) /* SYSENTER/SYSEXIT */
+#define X86_FEATURE_MTRR ( 0*32+12) /* Memory Type Range Registers */
+#define X86_FEATURE_PGE ( 0*32+13) /* Page Global Enable */
+#define X86_FEATURE_MCA ( 0*32+14) /* Machine Check Architecture */
+#define X86_FEATURE_CMOV ( 0*32+15) /* CMOV instructions */
/* (plus FCMOVcc, FCOMI with FPU) */
-#define X86_FEATURE_PAT ( 0*32+16) /* Page Attribute Table */
-#define X86_FEATURE_PSE36 ( 0*32+17) /* 36-bit PSEs */
-#define X86_FEATURE_PN ( 0*32+18) /* Processor serial number */
-#define X86_FEATURE_CLFLUSH ( 0*32+19) /* CLFLUSH instruction */
-#define X86_FEATURE_DS ( 0*32+21) /* "dts" Debug Store */
-#define X86_FEATURE_ACPI ( 0*32+22) /* ACPI via MSR */
-#define X86_FEATURE_MMX ( 0*32+23) /* Multimedia Extensions */
-#define X86_FEATURE_FXSR ( 0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */
-#define X86_FEATURE_XMM ( 0*32+25) /* "sse" */
-#define X86_FEATURE_XMM2 ( 0*32+26) /* "sse2" */
-#define X86_FEATURE_SELFSNOOP ( 0*32+27) /* "ss" CPU self snoop */
-#define X86_FEATURE_HT ( 0*32+28) /* Hyper-Threading */
-#define X86_FEATURE_ACC ( 0*32+29) /* "tm" Automatic clock control */
-#define X86_FEATURE_IA64 ( 0*32+30) /* IA-64 processor */
-#define X86_FEATURE_PBE ( 0*32+31) /* Pending Break Enable */
+#define X86_FEATURE_PAT ( 0*32+16) /* Page Attribute Table */
+#define X86_FEATURE_PSE36 ( 0*32+17) /* 36-bit PSEs */
+#define X86_FEATURE_PN ( 0*32+18) /* Processor serial number */
+#define X86_FEATURE_CLFLUSH ( 0*32+19) /* CLFLUSH instruction */
+#define X86_FEATURE_DS ( 0*32+21) /* "dts" Debug Store */
+#define X86_FEATURE_ACPI ( 0*32+22) /* ACPI via MSR */
+#define X86_FEATURE_MMX ( 0*32+23) /* Multimedia Extensions */
+#define X86_FEATURE_FXSR ( 0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */
+#define X86_FEATURE_XMM ( 0*32+25) /* "sse" */
+#define X86_FEATURE_XMM2 ( 0*32+26) /* "sse2" */
+#define X86_FEATURE_SELFSNOOP ( 0*32+27) /* "ss" CPU self snoop */
+#define X86_FEATURE_HT ( 0*32+28) /* Hyper-Threading */
+#define X86_FEATURE_ACC ( 0*32+29) /* "tm" Automatic clock control */
+#define X86_FEATURE_IA64 ( 0*32+30) /* IA-64 processor */
+#define X86_FEATURE_PBE ( 0*32+31) /* Pending Break Enable */
/* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
/* Don't duplicate feature flags which are redundant with Intel! */
-#define X86_FEATURE_SYSCALL ( 1*32+11) /* SYSCALL/SYSRET */
-#define X86_FEATURE_MP ( 1*32+19) /* MP Capable. */
-#define X86_FEATURE_NX ( 1*32+20) /* Execute Disable */
-#define X86_FEATURE_MMXEXT ( 1*32+22) /* AMD MMX extensions */
-#define X86_FEATURE_FXSR_OPT ( 1*32+25) /* FXSAVE/FXRSTOR optimizations */
-#define X86_FEATURE_GBPAGES ( 1*32+26) /* "pdpe1gb" GB pages */
-#define X86_FEATURE_RDTSCP ( 1*32+27) /* RDTSCP */
-#define X86_FEATURE_LM ( 1*32+29) /* Long Mode (x86-64) */
-#define X86_FEATURE_3DNOWEXT ( 1*32+30) /* AMD 3DNow! extensions */
-#define X86_FEATURE_3DNOW ( 1*32+31) /* 3DNow! */
+#define X86_FEATURE_SYSCALL ( 1*32+11) /* SYSCALL/SYSRET */
+#define X86_FEATURE_MP ( 1*32+19) /* MP Capable. */
+#define X86_FEATURE_NX ( 1*32+20) /* Execute Disable */
+#define X86_FEATURE_MMXEXT ( 1*32+22) /* AMD MMX extensions */
+#define X86_FEATURE_FXSR_OPT ( 1*32+25) /* FXSAVE/FXRSTOR optimizations */
+#define X86_FEATURE_GBPAGES ( 1*32+26) /* "pdpe1gb" GB pages */
+#define X86_FEATURE_RDTSCP ( 1*32+27) /* RDTSCP */
+#define X86_FEATURE_LM ( 1*32+29) /* Long Mode (x86-64) */
+#define X86_FEATURE_3DNOWEXT ( 1*32+30) /* AMD 3DNow! extensions */
+#define X86_FEATURE_3DNOW ( 1*32+31) /* 3DNow! */
/* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
-#define X86_FEATURE_RECOVERY ( 2*32+ 0) /* CPU in recovery mode */
-#define X86_FEATURE_LONGRUN ( 2*32+ 1) /* Longrun power control */
-#define X86_FEATURE_LRTI ( 2*32+ 3) /* LongRun table interface */
+#define X86_FEATURE_RECOVERY ( 2*32+ 0) /* CPU in recovery mode */
+#define X86_FEATURE_LONGRUN ( 2*32+ 1) /* Longrun power control */
+#define X86_FEATURE_LRTI ( 2*32+ 3) /* LongRun table interface */
/* Other features, Linux-defined mapping, word 3 */
/* This range is used for feature bits which conflict or are synthesized */
-#define X86_FEATURE_CXMMX ( 3*32+ 0) /* Cyrix MMX extensions */
-#define X86_FEATURE_K6_MTRR ( 3*32+ 1) /* AMD K6 nonstandard MTRRs */
-#define X86_FEATURE_CYRIX_ARR ( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */
-#define X86_FEATURE_CENTAUR_MCR ( 3*32+ 3) /* Centaur MCRs (= MTRRs) */
+#define X86_FEATURE_CXMMX ( 3*32+ 0) /* Cyrix MMX extensions */
+#define X86_FEATURE_K6_MTRR ( 3*32+ 1) /* AMD K6 nonstandard MTRRs */
+#define X86_FEATURE_CYRIX_ARR ( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */
+#define X86_FEATURE_CENTAUR_MCR ( 3*32+ 3) /* Centaur MCRs (= MTRRs) */
/* cpu types for specific tunings: */
-#define X86_FEATURE_K8 ( 3*32+ 4) /* "" Opteron, Athlon64 */
-#define X86_FEATURE_K7 ( 3*32+ 5) /* "" Athlon */
-#define X86_FEATURE_P3 ( 3*32+ 6) /* "" P3 */
-#define X86_FEATURE_P4 ( 3*32+ 7) /* "" P4 */
-#define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */
-#define X86_FEATURE_UP ( 3*32+ 9) /* smp kernel running on up */
-#define X86_FEATURE_ART ( 3*32+10) /* Platform has always running timer (ART) */
-#define X86_FEATURE_ARCH_PERFMON ( 3*32+11) /* Intel Architectural PerfMon */
-#define X86_FEATURE_PEBS ( 3*32+12) /* Precise-Event Based Sampling */
-#define X86_FEATURE_BTS ( 3*32+13) /* Branch Trace Store */
-#define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in ia32 userspace */
-#define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in ia32 userspace */
-#define X86_FEATURE_REP_GOOD ( 3*32+16) /* rep microcode works well */
-#define X86_FEATURE_MFENCE_RDTSC ( 3*32+17) /* "" Mfence synchronizes RDTSC */
-#define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" Lfence synchronizes RDTSC */
-#define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechanism */
-#define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */
-#define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */
-#define X86_FEATURE_XTOPOLOGY ( 3*32+22) /* cpu topology enum extensions */
-#define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */
-#define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */
-#define X86_FEATURE_CPUID ( 3*32+25) /* CPU has CPUID instruction itself */
-#define X86_FEATURE_EXTD_APICID ( 3*32+26) /* has extended APICID (8 bits) */
-#define X86_FEATURE_AMD_DCM ( 3*32+27) /* multi-node processor */
-#define X86_FEATURE_APERFMPERF ( 3*32+28) /* APERFMPERF */
-#define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */
-#define X86_FEATURE_TSC_KNOWN_FREQ ( 3*32+31) /* TSC has known frequency */
+#define X86_FEATURE_K8 ( 3*32+ 4) /* "" Opteron, Athlon64 */
+#define X86_FEATURE_K7 ( 3*32+ 5) /* "" Athlon */
+#define X86_FEATURE_P3 ( 3*32+ 6) /* "" P3 */
+#define X86_FEATURE_P4 ( 3*32+ 7) /* "" P4 */
+#define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */
+#define X86_FEATURE_UP ( 3*32+ 9) /* smp kernel running on up */
+#define X86_FEATURE_ART ( 3*32+10) /* Platform has always running timer (ART) */
+#define X86_FEATURE_ARCH_PERFMON ( 3*32+11) /* Intel Architectural PerfMon */
+#define X86_FEATURE_PEBS ( 3*32+12) /* Precise-Event Based Sampling */
+#define X86_FEATURE_BTS ( 3*32+13) /* Branch Trace Store */
+#define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in ia32 userspace */
+#define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in ia32 userspace */
+#define X86_FEATURE_REP_GOOD ( 3*32+16) /* rep microcode works well */
+#define X86_FEATURE_MFENCE_RDTSC ( 3*32+17) /* "" Mfence synchronizes RDTSC */
+#define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" Lfence synchronizes RDTSC */
+#define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechanism */
+#define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */
+#define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */
+#define X86_FEATURE_XTOPOLOGY ( 3*32+22) /* cpu topology enum extensions */
+#define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */
+#define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */
+#define X86_FEATURE_CPUID ( 3*32+25) /* CPU has CPUID instruction itself */
+#define X86_FEATURE_EXTD_APICID ( 3*32+26) /* has extended APICID (8 bits) */
+#define X86_FEATURE_AMD_DCM ( 3*32+27) /* multi-node processor */
+#define X86_FEATURE_APERFMPERF ( 3*32+28) /* APERFMPERF */
+#define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */
+#define X86_FEATURE_TSC_KNOWN_FREQ ( 3*32+31) /* TSC has known frequency */
/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
-#define X86_FEATURE_XMM3 ( 4*32+ 0) /* "pni" SSE-3 */
-#define X86_FEATURE_PCLMULQDQ ( 4*32+ 1) /* PCLMULQDQ instruction */
-#define X86_FEATURE_DTES64 ( 4*32+ 2) /* 64-bit Debug Store */
-#define X86_FEATURE_MWAIT ( 4*32+ 3) /* "monitor" Monitor/Mwait support */
-#define X86_FEATURE_DSCPL ( 4*32+ 4) /* "ds_cpl" CPL Qual. Debug Store */
-#define X86_FEATURE_VMX ( 4*32+ 5) /* Hardware virtualization */
-#define X86_FEATURE_SMX ( 4*32+ 6) /* Safer mode */
-#define X86_FEATURE_EST ( 4*32+ 7) /* Enhanced SpeedStep */
-#define X86_FEATURE_TM2 ( 4*32+ 8) /* Thermal Monitor 2 */
-#define X86_FEATURE_SSSE3 ( 4*32+ 9) /* Supplemental SSE-3 */
-#define X86_FEATURE_CID ( 4*32+10) /* Context ID */
-#define X86_FEATURE_SDBG ( 4*32+11) /* Silicon Debug */
-#define X86_FEATURE_FMA ( 4*32+12) /* Fused multiply-add */
-#define X86_FEATURE_CX16 ( 4*32+13) /* CMPXCHG16B */
-#define X86_FEATURE_XTPR ( 4*32+14) /* Send Task Priority Messages */
-#define X86_FEATURE_PDCM ( 4*32+15) /* Performance Capabilities */
-#define X86_FEATURE_PCID ( 4*32+17) /* Process Context Identifiers */
-#define X86_FEATURE_DCA ( 4*32+18) /* Direct Cache Access */
-#define X86_FEATURE_XMM4_1 ( 4*32+19) /* "sse4_1" SSE-4.1 */
-#define X86_FEATURE_XMM4_2 ( 4*32+20) /* "sse4_2" SSE-4.2 */
-#define X86_FEATURE_X2APIC ( 4*32+21) /* x2APIC */
-#define X86_FEATURE_MOVBE ( 4*32+22) /* MOVBE instruction */
-#define X86_FEATURE_POPCNT ( 4*32+23) /* POPCNT instruction */
+#define X86_FEATURE_XMM3 ( 4*32+ 0) /* "pni" SSE-3 */
+#define X86_FEATURE_PCLMULQDQ ( 4*32+ 1) /* PCLMULQDQ instruction */
+#define X86_FEATURE_DTES64 ( 4*32+ 2) /* 64-bit Debug Store */
+#define X86_FEATURE_MWAIT ( 4*32+ 3) /* "monitor" Monitor/Mwait support */
+#define X86_FEATURE_DSCPL ( 4*32+ 4) /* "ds_cpl" CPL Qual. Debug Store */
+#define X86_FEATURE_VMX ( 4*32+ 5) /* Hardware virtualization */
+#define X86_FEATURE_SMX ( 4*32+ 6) /* Safer mode */
+#define X86_FEATURE_EST ( 4*32+ 7) /* Enhanced SpeedStep */
+#define X86_FEATURE_TM2 ( 4*32+ 8) /* Thermal Monitor 2 */
+#define X86_FEATURE_SSSE3 ( 4*32+ 9) /* Supplemental SSE-3 */
+#define X86_FEATURE_CID ( 4*32+10) /* Context ID */
+#define X86_FEATURE_SDBG ( 4*32+11) /* Silicon Debug */
+#define X86_FEATURE_FMA ( 4*32+12) /* Fused multiply-add */
+#define X86_FEATURE_CX16 ( 4*32+13) /* CMPXCHG16B */
+#define X86_FEATURE_XTPR ( 4*32+14) /* Send Task Priority Messages */
+#define X86_FEATURE_PDCM ( 4*32+15) /* Performance Capabilities */
+#define X86_FEATURE_PCID ( 4*32+17) /* Process Context Identifiers */
+#define X86_FEATURE_DCA ( 4*32+18) /* Direct Cache Access */
+#define X86_FEATURE_XMM4_1 ( 4*32+19) /* "sse4_1" SSE-4.1 */
+#define X86_FEATURE_XMM4_2 ( 4*32+20) /* "sse4_2" SSE-4.2 */
+#define X86_FEATURE_X2APIC ( 4*32+21) /* x2APIC */
+#define X86_FEATURE_MOVBE ( 4*32+22) /* MOVBE instruction */
+#define X86_FEATURE_POPCNT ( 4*32+23) /* POPCNT instruction */
#define X86_FEATURE_TSC_DEADLINE_TIMER ( 4*32+24) /* Tsc deadline timer */
-#define X86_FEATURE_AES ( 4*32+25) /* AES instructions */
-#define X86_FEATURE_XSAVE ( 4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */
-#define X86_FEATURE_OSXSAVE ( 4*32+27) /* "" XSAVE enabled in the OS */
-#define X86_FEATURE_AVX ( 4*32+28) /* Advanced Vector Extensions */
-#define X86_FEATURE_F16C ( 4*32+29) /* 16-bit fp conversions */
-#define X86_FEATURE_RDRAND ( 4*32+30) /* The RDRAND instruction */
-#define X86_FEATURE_HYPERVISOR ( 4*32+31) /* Running on a hypervisor */
+#define X86_FEATURE_AES ( 4*32+25) /* AES instructions */
+#define X86_FEATURE_XSAVE ( 4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */
+#define X86_FEATURE_OSXSAVE ( 4*32+27) /* "" XSAVE enabled in the OS */
+#define X86_FEATURE_AVX ( 4*32+28) /* Advanced Vector Extensions */
+#define X86_FEATURE_F16C ( 4*32+29) /* 16-bit fp conversions */
+#define X86_FEATURE_RDRAND ( 4*32+30) /* The RDRAND instruction */
+#define X86_FEATURE_HYPERVISOR ( 4*32+31) /* Running on a hypervisor */
/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
-#define X86_FEATURE_XSTORE ( 5*32+ 2) /* "rng" RNG present (xstore) */
-#define X86_FEATURE_XSTORE_EN ( 5*32+ 3) /* "rng_en" RNG enabled */
-#define X86_FEATURE_XCRYPT ( 5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */
-#define X86_FEATURE_XCRYPT_EN ( 5*32+ 7) /* "ace_en" on-CPU crypto enabled */
-#define X86_FEATURE_ACE2 ( 5*32+ 8) /* Advanced Cryptography Engine v2 */
-#define X86_FEATURE_ACE2_EN ( 5*32+ 9) /* ACE v2 enabled */
-#define X86_FEATURE_PHE ( 5*32+10) /* PadLock Hash Engine */
-#define X86_FEATURE_PHE_EN ( 5*32+11) /* PHE enabled */
-#define X86_FEATURE_PMM ( 5*32+12) /* PadLock Montgomery Multiplier */
-#define X86_FEATURE_PMM_EN ( 5*32+13) /* PMM enabled */
+#define X86_FEATURE_XSTORE ( 5*32+ 2) /* "rng" RNG present (xstore) */
+#define X86_FEATURE_XSTORE_EN ( 5*32+ 3) /* "rng_en" RNG enabled */
+#define X86_FEATURE_XCRYPT ( 5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */
+#define X86_FEATURE_XCRYPT_EN ( 5*32+ 7) /* "ace_en" on-CPU crypto enabled */
+#define X86_FEATURE_ACE2 ( 5*32+ 8) /* Advanced Cryptography Engine v2 */
+#define X86_FEATURE_ACE2_EN ( 5*32+ 9) /* ACE v2 enabled */
+#define X86_FEATURE_PHE ( 5*32+10) /* PadLock Hash Engine */
+#define X86_FEATURE_PHE_EN ( 5*32+11) /* PHE enabled */
+#define X86_FEATURE_PMM ( 5*32+12) /* PadLock Montgomery Multiplier */
+#define X86_FEATURE_PMM_EN ( 5*32+13) /* PMM enabled */
/* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */
-#define X86_FEATURE_LAHF_LM ( 6*32+ 0) /* LAHF/SAHF in long mode */
-#define X86_FEATURE_CMP_LEGACY ( 6*32+ 1) /* If yes HyperThreading not valid */
-#define X86_FEATURE_SVM ( 6*32+ 2) /* Secure virtual machine */
-#define X86_FEATURE_EXTAPIC ( 6*32+ 3) /* Extended APIC space */
-#define X86_FEATURE_CR8_LEGACY ( 6*32+ 4) /* CR8 in 32-bit mode */
-#define X86_FEATURE_ABM ( 6*32+ 5) /* Advanced bit manipulation */
-#define X86_FEATURE_SSE4A ( 6*32+ 6) /* SSE-4A */
-#define X86_FEATURE_MISALIGNSSE ( 6*32+ 7) /* Misaligned SSE mode */
-#define X86_FEATURE_3DNOWPREFETCH ( 6*32+ 8) /* 3DNow prefetch instructions */
-#define X86_FEATURE_OSVW ( 6*32+ 9) /* OS Visible Workaround */
-#define X86_FEATURE_IBS ( 6*32+10) /* Instruction Based Sampling */
-#define X86_FEATURE_XOP ( 6*32+11) /* extended AVX instructions */
-#define X86_FEATURE_SKINIT ( 6*32+12) /* SKINIT/STGI instructions */
-#define X86_FEATURE_WDT ( 6*32+13) /* Watchdog timer */
-#define X86_FEATURE_LWP ( 6*32+15) /* Light Weight Profiling */
-#define X86_FEATURE_FMA4 ( 6*32+16) /* 4 operands MAC instructions */
-#define X86_FEATURE_TCE ( 6*32+17) /* translation cache extension */
-#define X86_FEATURE_NODEID_MSR ( 6*32+19) /* NodeId MSR */
-#define X86_FEATURE_TBM ( 6*32+21) /* trailing bit manipulations */
-#define X86_FEATURE_TOPOEXT ( 6*32+22) /* topology extensions CPUID leafs */
-#define X86_FEATURE_PERFCTR_CORE ( 6*32+23) /* core performance counter extensions */
-#define X86_FEATURE_PERFCTR_NB ( 6*32+24) /* NB performance counter extensions */
-#define X86_FEATURE_BPEXT (6*32+26) /* data breakpoint extension */
-#define X86_FEATURE_PTSC ( 6*32+27) /* performance time-stamp counter */
-#define X86_FEATURE_PERFCTR_LLC ( 6*32+28) /* Last Level Cache performance counter extensions */
-#define X86_FEATURE_MWAITX ( 6*32+29) /* MWAIT extension (MONITORX/MWAITX) */
+#define X86_FEATURE_LAHF_LM ( 6*32+ 0) /* LAHF/SAHF in long mode */
+#define X86_FEATURE_CMP_LEGACY ( 6*32+ 1) /* If yes HyperThreading not valid */
+#define X86_FEATURE_SVM ( 6*32+ 2) /* Secure virtual machine */
+#define X86_FEATURE_EXTAPIC ( 6*32+ 3) /* Extended APIC space */
+#define X86_FEATURE_CR8_LEGACY ( 6*32+ 4) /* CR8 in 32-bit mode */
+#define X86_FEATURE_ABM ( 6*32+ 5) /* Advanced bit manipulation */
+#define X86_FEATURE_SSE4A ( 6*32+ 6) /* SSE-4A */
+#define X86_FEATURE_MISALIGNSSE ( 6*32+ 7) /* Misaligned SSE mode */
+#define X86_FEATURE_3DNOWPREFETCH ( 6*32+ 8) /* 3DNow prefetch instructions */
+#define X86_FEATURE_OSVW ( 6*32+ 9) /* OS Visible Workaround */
+#define X86_FEATURE_IBS ( 6*32+10) /* Instruction Based Sampling */
+#define X86_FEATURE_XOP ( 6*32+11) /* extended AVX instructions */
+#define X86_FEATURE_SKINIT ( 6*32+12) /* SKINIT/STGI instructions */
+#define X86_FEATURE_WDT ( 6*32+13) /* Watchdog timer */
+#define X86_FEATURE_LWP ( 6*32+15) /* Light Weight Profiling */
+#define X86_FEATURE_FMA4 ( 6*32+16) /* 4 operands MAC instructions */
+#define X86_FEATURE_TCE ( 6*32+17) /* translation cache extension */
+#define X86_FEATURE_NODEID_MSR ( 6*32+19) /* NodeId MSR */
+#define X86_FEATURE_TBM ( 6*32+21) /* trailing bit manipulations */
+#define X86_FEATURE_TOPOEXT ( 6*32+22) /* topology extensions CPUID leafs */
+#define X86_FEATURE_PERFCTR_CORE ( 6*32+23) /* core performance counter extensions */
+#define X86_FEATURE_PERFCTR_NB ( 6*32+24) /* NB performance counter extensions */
+#define X86_FEATURE_BPEXT (6*32+26) /* data breakpoint extension */
+#define X86_FEATURE_PTSC ( 6*32+27) /* performance time-stamp counter */
+#define X86_FEATURE_PERFCTR_LLC ( 6*32+28) /* Last Level Cache performance counter extensions */
+#define X86_FEATURE_MWAITX ( 6*32+29) /* MWAIT extension (MONITORX/MWAITX) */
/*
* Auxiliary flags: Linux defined - For features scattered in various
@@ -192,152 +192,152 @@
*
* Reuse free bits when adding new feature flags!
*/
-#define X86_FEATURE_RING3MWAIT ( 7*32+ 0) /* Ring 3 MONITOR/MWAIT */
-#define X86_FEATURE_CPUID_FAULT ( 7*32+ 1) /* Intel CPUID faulting */
-#define X86_FEATURE_CPB ( 7*32+ 2) /* AMD Core Performance Boost */
-#define X86_FEATURE_EPB ( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */
-#define X86_FEATURE_CAT_L3 ( 7*32+ 4) /* Cache Allocation Technology L3 */
-#define X86_FEATURE_CAT_L2 ( 7*32+ 5) /* Cache Allocation Technology L2 */
-#define X86_FEATURE_CDP_L3 ( 7*32+ 6) /* Code and Data Prioritization L3 */
-
-#define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */
-#define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */
-#define X86_FEATURE_SME ( 7*32+10) /* AMD Secure Memory Encryption */
-
-#define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */
-#define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */
-#define X86_FEATURE_AVX512_4VNNIW (7*32+16) /* AVX-512 Neural Network Instructions */
-#define X86_FEATURE_AVX512_4FMAPS (7*32+17) /* AVX-512 Multiply Accumulation Single precision */
+#define X86_FEATURE_RING3MWAIT ( 7*32+ 0) /* Ring 3 MONITOR/MWAIT */
+#define X86_FEATURE_CPUID_FAULT ( 7*32+ 1) /* Intel CPUID faulting */
+#define X86_FEATURE_CPB ( 7*32+ 2) /* AMD Core Performance Boost */
+#define X86_FEATURE_EPB ( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */
+#define X86_FEATURE_CAT_L3 ( 7*32+ 4) /* Cache Allocation Technology L3 */
+#define X86_FEATURE_CAT_L2 ( 7*32+ 5) /* Cache Allocation Technology L2 */
+#define X86_FEATURE_CDP_L3 ( 7*32+ 6) /* Code and Data Prioritization L3 */
+
+#define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */
+#define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */
+#define X86_FEATURE_SME ( 7*32+10) /* AMD Secure Memory Encryption */
+
+#define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */
+#define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */
+#define X86_FEATURE_AVX512_4VNNIW (7*32+16) /* AVX-512 Neural Network Instructions */
+#define X86_FEATURE_AVX512_4FMAPS (7*32+17) /* AVX-512 Multiply Accumulation Single precision */
-#define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */
+#define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */
/* Virtualization flags: Linux defined, word 8 */
-#define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */
-#define X86_FEATURE_VNMI ( 8*32+ 1) /* Intel Virtual NMI */
-#define X86_FEATURE_FLEXPRIORITY ( 8*32+ 2) /* Intel FlexPriority */
-#define X86_FEATURE_EPT ( 8*32+ 3) /* Intel Extended Page Table */
-#define X86_FEATURE_VPID ( 8*32+ 4) /* Intel Virtual Processor ID */
+#define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */
+#define X86_FEATURE_VNMI ( 8*32+ 1) /* Intel Virtual NMI */
+#define X86_FEATURE_FLEXPRIORITY ( 8*32+ 2) /* Intel FlexPriority */
+#define X86_FEATURE_EPT ( 8*32+ 3) /* Intel Extended Page Table */
+#define X86_FEATURE_VPID ( 8*32+ 4) /* Intel Virtual Processor ID */
-#define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer vmmcall to vmcall */
-#define X86_FEATURE_XENPV ( 8*32+16) /* "" Xen paravirtual guest */
+#define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer vmmcall to vmcall */
+#define X86_FEATURE_XENPV ( 8*32+16) /* "" Xen paravirtual guest */
/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */
-#define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/
-#define X86_FEATURE_TSC_ADJUST ( 9*32+ 1) /* TSC adjustment MSR 0x3b */
-#define X86_FEATURE_BMI1 ( 9*32+ 3) /* 1st group bit manipulation extensions */
-#define X86_FEATURE_HLE ( 9*32+ 4) /* Hardware Lock Elision */
-#define X86_FEATURE_AVX2 ( 9*32+ 5) /* AVX2 instructions */
-#define X86_FEATURE_SMEP ( 9*32+ 7) /* Supervisor Mode Execution Protection */
-#define X86_FEATURE_BMI2 ( 9*32+ 8) /* 2nd group bit manipulation extensions */
-#define X86_FEATURE_ERMS ( 9*32+ 9) /* Enhanced REP MOVSB/STOSB */
-#define X86_FEATURE_INVPCID ( 9*32+10) /* Invalidate Processor Context ID */
-#define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional Memory */
-#define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */
-#define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection Extension */
-#define X86_FEATURE_RDT_A ( 9*32+15) /* Resource Director Technology Allocation */
-#define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */
-#define X86_FEATURE_AVX512DQ ( 9*32+17) /* AVX-512 DQ (Double/Quad granular) Instructions */
-#define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */
-#define X86_FEATURE_ADX ( 9*32+19) /* The ADCX and ADOX instructions */
-#define X86_FEATURE_SMAP ( 9*32+20) /* Supervisor Mode Access Prevention */
-#define X86_FEATURE_AVX512IFMA ( 9*32+21) /* AVX-512 Integer Fused Multiply-Add instructions */
-#define X86_FEATURE_CLFLUSHOPT ( 9*32+23) /* CLFLUSHOPT instruction */
-#define X86_FEATURE_CLWB ( 9*32+24) /* CLWB instruction */
-#define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */
-#define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */
-#define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */
-#define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */
-#define X86_FEATURE_AVX512BW ( 9*32+30) /* AVX-512 BW (Byte/Word granular) Instructions */
-#define X86_FEATURE_AVX512VL ( 9*32+31) /* AVX-512 VL (128/256 Vector Length) Extensions */
+#define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/
+#define X86_FEATURE_TSC_ADJUST ( 9*32+ 1) /* TSC adjustment MSR 0x3b */
+#define X86_FEATURE_BMI1 ( 9*32+ 3) /* 1st group bit manipulation extensions */
+#define X86_FEATURE_HLE ( 9*32+ 4) /* Hardware Lock Elision */
+#define X86_FEATURE_AVX2 ( 9*32+ 5) /* AVX2 instructions */
+#define X86_FEATURE_SMEP ( 9*32+ 7) /* Supervisor Mode Execution Protection */
+#define X86_FEATURE_BMI2 ( 9*32+ 8) /* 2nd group bit manipulation extensions */
+#define X86_FEATURE_ERMS ( 9*32+ 9) /* Enhanced REP MOVSB/STOSB */
+#define X86_FEATURE_INVPCID ( 9*32+10) /* Invalidate Processor Context ID */
+#define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional Memory */
+#define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */
+#define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection Extension */
+#define X86_FEATURE_RDT_A ( 9*32+15) /* Resource Director Technology Allocation */
+#define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */
+#define X86_FEATURE_AVX512DQ ( 9*32+17) /* AVX-512 DQ (Double/Quad granular) Instructions */
+#define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */
+#define X86_FEATURE_ADX ( 9*32+19) /* The ADCX and ADOX instructions */
+#define X86_FEATURE_SMAP ( 9*32+20) /* Supervisor Mode Access Prevention */
+#define X86_FEATURE_AVX512IFMA ( 9*32+21) /* AVX-512 Integer Fused Multiply-Add instructions */
+#define X86_FEATURE_CLFLUSHOPT ( 9*32+23) /* CLFLUSHOPT instruction */
+#define X86_FEATURE_CLWB ( 9*32+24) /* CLWB instruction */
+#define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */
+#define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */
+#define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */
+#define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */
+#define X86_FEATURE_AVX512BW ( 9*32+30) /* AVX-512 BW (Byte/Word granular) Instructions */
+#define X86_FEATURE_AVX512VL ( 9*32+31) /* AVX-512 VL (128/256 Vector Length) Extensions */
/* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */
-#define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */
-#define X86_FEATURE_XSAVEC (10*32+ 1) /* XSAVEC */
-#define X86_FEATURE_XGETBV1 (10*32+ 2) /* XGETBV with ECX = 1 */
-#define X86_FEATURE_XSAVES (10*32+ 3) /* XSAVES/XRSTORS */
+#define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */
+#define X86_FEATURE_XSAVEC (10*32+ 1) /* XSAVEC */
+#define X86_FEATURE_XGETBV1 (10*32+ 2) /* XGETBV with ECX = 1 */
+#define X86_FEATURE_XSAVES (10*32+ 3) /* XSAVES/XRSTORS */
/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:0 (edx), word 11 */
-#define X86_FEATURE_CQM_LLC (11*32+ 1) /* LLC QoS if 1 */
+#define X86_FEATURE_CQM_LLC (11*32+ 1) /* LLC QoS if 1 */
/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (edx), word 12 */
-#define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring if 1 */
-#define X86_FEATURE_CQM_MBM_TOTAL (12*32+ 1) /* LLC Total MBM monitoring */
-#define X86_FEATURE_CQM_MBM_LOCAL (12*32+ 2) /* LLC Local MBM monitoring */
+#define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring if 1 */
+#define X86_FEATURE_CQM_MBM_TOTAL (12*32+ 1) /* LLC Total MBM monitoring */
+#define X86_FEATURE_CQM_MBM_LOCAL (12*32+ 2) /* LLC Local MBM monitoring */
/* AMD-defined CPU features, CPUID level 0x80000008 (ebx), word 13 */
-#define X86_FEATURE_CLZERO (13*32+0) /* CLZERO instruction */
-#define X86_FEATURE_IRPERF (13*32+1) /* Instructions Retired Count */
+#define X86_FEATURE_CLZERO (13*32+0) /* CLZERO instruction */
+#define X86_FEATURE_IRPERF (13*32+1) /* Instructions Retired Count */
/* Thermal and Power Management Leaf, CPUID level 0x00000006 (eax), word 14 */
-#define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */
-#define X86_FEATURE_IDA (14*32+ 1) /* Intel Dynamic Acceleration */
-#define X86_FEATURE_ARAT (14*32+ 2) /* Always Running APIC Timer */
-#define X86_FEATURE_PLN (14*32+ 4) /* Intel Power Limit Notification */
-#define X86_FEATURE_PTS (14*32+ 6) /* Intel Package Thermal Status */
-#define X86_FEATURE_HWP (14*32+ 7) /* Intel Hardware P-states */
-#define X86_FEATURE_HWP_NOTIFY (14*32+ 8) /* HWP Notification */
-#define X86_FEATURE_HWP_ACT_WINDOW (14*32+ 9) /* HWP Activity Window */
-#define X86_FEATURE_HWP_EPP (14*32+10) /* HWP Energy Perf. Preference */
-#define X86_FEATURE_HWP_PKG_REQ (14*32+11) /* HWP Package Level Request */
+#define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */
+#define X86_FEATURE_IDA (14*32+ 1) /* Intel Dynamic Acceleration */
+#define X86_FEATURE_ARAT (14*32+ 2) /* Always Running APIC Timer */
+#define X86_FEATURE_PLN (14*32+ 4) /* Intel Power Limit Notification */
+#define X86_FEATURE_PTS (14*32+ 6) /* Intel Package Thermal Status */
+#define X86_FEATURE_HWP (14*32+ 7) /* Intel Hardware P-states */
+#define X86_FEATURE_HWP_NOTIFY (14*32+ 8) /* HWP Notification */
+#define X86_FEATURE_HWP_ACT_WINDOW (14*32+ 9) /* HWP Activity Window */
+#define X86_FEATURE_HWP_EPP (14*32+10) /* HWP Energy Perf. Preference */
+#define X86_FEATURE_HWP_PKG_REQ (14*32+11) /* HWP Package Level Request */
/* AMD SVM Feature Identification, CPUID level 0x8000000a (edx), word 15 */
-#define X86_FEATURE_NPT (15*32+ 0) /* Nested Page Table support */
-#define X86_FEATURE_LBRV (15*32+ 1) /* LBR Virtualization support */
-#define X86_FEATURE_SVML (15*32+ 2) /* "svm_lock" SVM locking MSR */
-#define X86_FEATURE_NRIPS (15*32+ 3) /* "nrip_save" SVM next_rip save */
-#define X86_FEATURE_TSCRATEMSR (15*32+ 4) /* "tsc_scale" TSC scaling support */
-#define X86_FEATURE_VMCBCLEAN (15*32+ 5) /* "vmcb_clean" VMCB clean bits support */
-#define X86_FEATURE_FLUSHBYASID (15*32+ 6) /* flush-by-ASID support */
-#define X86_FEATURE_DECODEASSISTS (15*32+ 7) /* Decode Assists support */
-#define X86_FEATURE_PAUSEFILTER (15*32+10) /* filtered pause intercept */
-#define X86_FEATURE_PFTHRESHOLD (15*32+12) /* pause filter threshold */
-#define X86_FEATURE_AVIC (15*32+13) /* Virtual Interrupt Controller */
-#define X86_FEATURE_V_VMSAVE_VMLOAD (15*32+15) /* Virtual VMSAVE VMLOAD */
-#define X86_FEATURE_VGIF (15*32+16) /* Virtual GIF */
+#define X86_FEATURE_NPT (15*32+ 0) /* Nested Page Table support */
+#define X86_FEATURE_LBRV (15*32+ 1) /* LBR Virtualization support */
+#define X86_FEATURE_SVML (15*32+ 2) /* "svm_lock" SVM locking MSR */
+#define X86_FEATURE_NRIPS (15*32+ 3) /* "nrip_save" SVM next_rip save */
+#define X86_FEATURE_TSCRATEMSR (15*32+ 4) /* "tsc_scale" TSC scaling support */
+#define X86_FEATURE_VMCBCLEAN (15*32+ 5) /* "vmcb_clean" VMCB clean bits support */
+#define X86_FEATURE_FLUSHBYASID (15*32+ 6) /* flush-by-ASID support */
+#define X86_FEATURE_DECODEASSISTS (15*32+ 7) /* Decode Assists support */
+#define X86_FEATURE_PAUSEFILTER (15*32+10) /* filtered pause intercept */
+#define X86_FEATURE_PFTHRESHOLD (15*32+12) /* pause filter threshold */
+#define X86_FEATURE_AVIC (15*32+13) /* Virtual Interrupt Controller */
+#define X86_FEATURE_V_VMSAVE_VMLOAD (15*32+15) /* Virtual VMSAVE VMLOAD */
+#define X86_FEATURE_VGIF (15*32+16) /* Virtual GIF */
/* Intel-defined CPU features, CPUID level 0x00000007:0 (ecx), word 16 */
-#define X86_FEATURE_AVX512VBMI (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/
-#define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */
-#define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */
-#define X86_FEATURE_AVX512_VBMI2 (16*32+ 6) /* Additional AVX512 Vector Bit Manipulation Instructions */
-#define X86_FEATURE_GFNI (16*32+ 8) /* Galois Field New Instructions */
-#define X86_FEATURE_VAES (16*32+ 9) /* Vector AES */
-#define X86_FEATURE_VPCLMULQDQ (16*32+ 10) /* Carry-Less Multiplication Double Quadword */
-#define X86_FEATURE_AVX512_VNNI (16*32+ 11) /* Vector Neural Network Instructions */
-#define X86_FEATURE_AVX512_BITALG (16*32+12) /* Support for VPOPCNT[B,W] and VPSHUF-BITQMB */
-#define X86_FEATURE_AVX512_VPOPCNTDQ (16*32+14) /* POPCNT for vectors of DW/QW */
-#define X86_FEATURE_LA57 (16*32+16) /* 5-level page tables */
-#define X86_FEATURE_RDPID (16*32+22) /* RDPID instruction */
+#define X86_FEATURE_AVX512VBMI (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/
+#define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */
+#define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */
+#define X86_FEATURE_AVX512_VBMI2 (16*32+ 6) /* Additional AVX512 Vector Bit Manipulation Instructions */
+#define X86_FEATURE_GFNI (16*32+ 8) /* Galois Field New Instructions */
+#define X86_FEATURE_VAES (16*32+ 9) /* Vector AES */
+#define X86_FEATURE_VPCLMULQDQ (16*32+ 10) /* Carry-Less Multiplication Double Quadword */
+#define X86_FEATURE_AVX512_VNNI (16*32+ 11) /* Vector Neural Network Instructions */
+#define X86_FEATURE_AVX512_BITALG (16*32+12) /* Support for VPOPCNT[B,W] and VPSHUF-BITQMB */
+#define X86_FEATURE_AVX512_VPOPCNTDQ (16*32+14) /* POPCNT for vectors of DW/QW */
+#define X86_FEATURE_LA57 (16*32+16) /* 5-level page tables */
+#define X86_FEATURE_RDPID (16*32+22) /* RDPID instruction */
/* AMD-defined CPU features, CPUID level 0x80000007 (ebx), word 17 */
-#define X86_FEATURE_OVERFLOW_RECOV (17*32+0) /* MCA overflow recovery support */
-#define X86_FEATURE_SUCCOR (17*32+1) /* Uncorrectable error containment and recovery */
-#define X86_FEATURE_SMCA (17*32+3) /* Scalable MCA */
+#define X86_FEATURE_OVERFLOW_RECOV (17*32+0) /* MCA overflow recovery support */
+#define X86_FEATURE_SUCCOR (17*32+1) /* Uncorrectable error containment and recovery */
+#define X86_FEATURE_SMCA (17*32+3) /* Scalable MCA */
/*
* BUG word(s)
*/
-#define X86_BUG(x) (NCAPINTS*32 + (x))
+#define X86_BUG(x) (NCAPINTS*32 + (x))
-#define X86_BUG_F00F X86_BUG(0) /* Intel F00F */
-#define X86_BUG_FDIV X86_BUG(1) /* FPU FDIV */
-#define X86_BUG_COMA X86_BUG(2) /* Cyrix 6x86 coma */
-#define X86_BUG_AMD_TLB_MMATCH X86_BUG(3) /* "tlb_mmatch" AMD Erratum 383 */
-#define X86_BUG_AMD_APIC_C1E X86_BUG(4) /* "apic_c1e" AMD Erratum 400 */
-#define X86_BUG_11AP X86_BUG(5) /* Bad local APIC aka 11AP */
-#define X86_BUG_FXSAVE_LEAK X86_BUG(6) /* FXSAVE leaks FOP/FIP/FOP */
-#define X86_BUG_CLFLUSH_MONITOR X86_BUG(7) /* AAI65, CLFLUSH required before MONITOR */
-#define X86_BUG_SYSRET_SS_ATTRS X86_BUG(8) /* SYSRET doesn't fix up SS attrs */
+#define X86_BUG_F00F X86_BUG(0) /* Intel F00F */
+#define X86_BUG_FDIV X86_BUG(1) /* FPU FDIV */
+#define X86_BUG_COMA X86_BUG(2) /* Cyrix 6x86 coma */
+#define X86_BUG_AMD_TLB_MMATCH X86_BUG(3) /* "tlb_mmatch" AMD Erratum 383 */
+#define X86_BUG_AMD_APIC_C1E X86_BUG(4) /* "apic_c1e" AMD Erratum 400 */
+#define X86_BUG_11AP X86_BUG(5) /* Bad local APIC aka 11AP */
+#define X86_BUG_FXSAVE_LEAK X86_BUG(6) /* FXSAVE leaks FOP/FIP/FOP */
+#define X86_BUG_CLFLUSH_MONITOR X86_BUG(7) /* AAI65, CLFLUSH required before MONITOR */
+#define X86_BUG_SYSRET_SS_ATTRS X86_BUG(8) /* SYSRET doesn't fix up SS attrs */
#ifdef CONFIG_X86_32
/*
* 64-bit kernels don't use X86_BUG_ESPFIX. Make the define conditional
* to avoid confusion.
*/
-#define X86_BUG_ESPFIX X86_BUG(9) /* "" IRET to 16-bit SS corrupts ESP/RSP high bits */
+#define X86_BUG_ESPFIX X86_BUG(9) /* "" IRET to 16-bit SS corrupts ESP/RSP high bits */
#endif
-#define X86_BUG_NULL_SEG X86_BUG(10) /* Nulling a selector preserves the base */
-#define X86_BUG_SWAPGS_FENCE X86_BUG(11) /* SWAPGS without input dep on GS */
-#define X86_BUG_MONITOR X86_BUG(12) /* IPI required to wake up remote CPU */
-#define X86_BUG_AMD_E400 X86_BUG(13) /* CPU is among the affected by Erratum 400 */
+#define X86_BUG_NULL_SEG X86_BUG(10) /* Nulling a selector preserves the base */
+#define X86_BUG_SWAPGS_FENCE X86_BUG(11) /* SWAPGS without input dep on GS */
+#define X86_BUG_MONITOR X86_BUG(12) /* IPI required to wake up remote CPU */
+#define X86_BUG_AMD_E400 X86_BUG(13) /* CPU is among the affected by Erratum 400 */
#endif /* _ASM_X86_CPUFEATURES_H */
next prev parent reply other threads:[~2017-12-22 8:45 UTC|newest]
Thread overview: 234+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-12-22 8:44 [PATCH 4.14 000/159] 4.14.9-stable review Greg Kroah-Hartman
2017-12-22 8:44 ` [PATCH 4.14 001/159] x86/asm: Remove unnecessary \n\t in front of CC_SET() from asm templates Greg Kroah-Hartman
2017-12-22 8:44 ` [PATCH 4.14 002/159] objtool: Dont report end of section error after an empty unwind hint Greg Kroah-Hartman
2017-12-22 8:44 ` [PATCH 4.14 003/159] x86/head: Remove confusing comment Greg Kroah-Hartman
2017-12-22 8:44 ` [PATCH 4.14 004/159] x86/head: Remove unused bad_address code Greg Kroah-Hartman
2017-12-22 8:44 ` [PATCH 4.14 005/159] x86/head: Fix head ELF function annotations Greg Kroah-Hartman
2017-12-22 8:44 ` [PATCH 4.14 006/159] x86/boot: Annotate verify_cpu() as a callable function Greg Kroah-Hartman
2017-12-22 8:44 ` [PATCH 4.14 007/159] x86/xen: Fix xen head ELF annotations Greg Kroah-Hartman
2017-12-22 8:44 ` [PATCH 4.14 008/159] x86/xen: Add unwind hint annotations Greg Kroah-Hartman
2017-12-22 8:44 ` [PATCH 4.14 009/159] x86/head: " Greg Kroah-Hartman
2017-12-22 8:44 ` [PATCH 4.14 010/159] ACPI / APEI: adjust a local variable type in ghes_ioremap_pfn_irq() Greg Kroah-Hartman
2017-12-22 8:44 ` [PATCH 4.14 011/159] x86/unwinder: Make CONFIG_UNWINDER_ORC=y the default in the 64-bit defconfig Greg Kroah-Hartman
2017-12-22 8:44 ` [PATCH 4.14 012/159] x86/fpu/debug: Remove unused x86_fpu_state and x86_fpu_deactivate_state tracepoints Greg Kroah-Hartman
2017-12-22 8:44 ` [PATCH 4.14 013/159] x86/unwind: Rename unwinder config options to CONFIG_UNWINDER_* Greg Kroah-Hartman
2017-12-22 8:44 ` [PATCH 4.14 014/159] x86/unwind: Make CONFIG_UNWINDER_ORC=y the default in kconfig for 64-bit Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 015/159] bitops: Add clear/set_bit32() to linux/bitops.h Greg Kroah-Hartman
2017-12-26 21:41 ` Ben Hutchings
2017-12-27 12:48 ` Greg Kroah-Hartman
2017-12-27 19:40 ` Ben Hutchings
2017-12-22 8:45 ` [PATCH 4.14 016/159] x86/cpuid: Add generic table for CPUID dependencies Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 017/159] x86/fpu: Parse clearcpuid= as early XSAVE argument Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 018/159] x86/fpu: Make XSAVE check the base CPUID features before enabling Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 019/159] x86/fpu: Remove the explicit clearing of XSAVE dependent features Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 020/159] x86/platform/UV: Convert timers to use timer_setup() Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 021/159] objtool: Print top level commands on incorrect usage Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 022/159] x86/cpuid: Prevent out of bound access in do_clear_cpu_cap() Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 023/159] mm/sparsemem: Allocate mem_section at runtime for CONFIG_SPARSEMEM_EXTREME=y Greg Kroah-Hartman
2017-12-22 14:18 ` Dan Rue
2017-12-22 14:52 ` Naresh Kamboju
2017-12-22 15:12 ` Greg Kroah-Hartman
2017-12-22 15:03 ` Greg Kroah-Hartman
2018-01-07 5:14 ` Mike Galbraith
2018-01-07 9:11 ` Greg Kroah-Hartman
2018-01-07 9:21 ` Mike Galbraith
2018-01-07 10:18 ` Michal Hocko
2018-01-07 10:42 ` Greg Kroah-Hartman
2018-01-07 12:44 ` Mike Galbraith
2018-01-07 13:23 ` Michal Hocko
2018-01-08 7:53 ` Greg Kroah-Hartman
2018-01-08 8:15 ` Mike Galbraith
2018-01-08 8:33 ` Greg Kroah-Hartman
2018-01-08 9:45 ` Mike Galbraith
2018-01-08 8:47 ` Michal Hocko
2018-01-08 9:10 ` Greg Kroah-Hartman
2018-01-08 9:27 ` Greg Kroah-Hartman
2018-01-08 16:04 ` Ingo Molnar
2018-01-08 17:46 ` Kirill A. Shutemov
2018-01-09 0:13 ` Kirill A. Shutemov
2018-01-09 1:09 ` Dave Young
2018-01-09 5:41 ` Baoquan He
2018-01-09 7:24 ` Dave Young
2018-01-09 9:05 ` Kirill A. Shutemov
2018-01-10 3:08 ` Dave Young
2018-01-10 11:16 ` Kirill A. Shutemov
2018-01-11 1:06 ` Baoquan He
2018-01-12 0:55 ` Dave Young
2018-01-15 5:57 ` Omar Sandoval
2018-01-16 8:36 ` Atsushi Kumagai
2018-01-09 3:44 ` Mike Galbraith
2018-02-07 9:25 ` Dou Liyang
2018-02-07 10:41 ` Kirill A. Shutemov
2018-02-07 10:45 ` Mike Galbraith
2018-02-07 12:00 ` Dou Liyang
2018-02-07 12:08 ` Baoquan He
2018-02-07 12:17 ` Dou Liyang
2018-02-07 12:27 ` Baoquan He
2018-02-07 12:34 ` Dou Liyang
2018-02-07 12:45 ` Baoquan He
2018-02-08 1:14 ` Dou Liyang
2018-02-08 1:23 ` Baoquan He
2018-02-08 1:44 ` Dou Liyang
2018-02-07 11:28 ` Baoquan He
2018-01-17 5:24 ` Baoquan He
2018-01-25 15:50 ` Kirill A. Shutemov
2018-01-26 2:48 ` Baoquan He
2017-12-22 8:45 ` [PATCH 4.14 024/159] x86/kasan: Use the same shadow offset for 4- and 5-level paging Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 025/159] x86/xen: Provide pre-built page tables only for CONFIG_XEN_PV=y and CONFIG_XEN_PVH=y Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 026/159] x86/xen: Drop 5-level paging support code from the XEN_PV code Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 027/159] ACPI / APEI: remove the unused dead-code for SEA/NMI notification type Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 028/159] x86/asm: Dont use the confusing .ifeq directive Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 029/159] x86/build: Beautify build log of syscall headers Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 030/159] x86/mm/64: Rename the register_page_bootmem_memmap() size parameter to nr_pages Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 031/159] x86/cpufeatures: Enable new SSE/AVX/AVX512 CPU features Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 032/159] x86/mm: Relocate page fault error codes to traps.h Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 033/159] x86/boot: Relocate definition of the initial state of CR0 Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 034/159] ptrace,x86: Make user_64bit_mode() available to 32-bit builds Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 035/159] x86/entry/64: Remove the restore_c_regs_and_iret label Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 036/159] x86/entry/64: Split the IRET-to-user and IRET-to-kernel paths Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 037/159] x86/entry/64: Move SWAPGS into the common IRET-to-usermode path Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 038/159] x86/entry/64: Simplify reg restore code in the standard IRET paths Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 039/159] x86/entry/64: Shrink paranoid_exit_restore and make labels local Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 040/159] x86/entry/64: Use pop instead of movq in syscall_return_via_sysret Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 041/159] x86/entry/64: Merge the fast and slow SYSRET paths Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 042/159] x86/entry/64: Use POP instead of MOV to restore regs on NMI return Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 043/159] x86/entry/64: Remove the RESTORE_..._REGS infrastructure Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 044/159] xen, x86/entry/64: Add xen NMI trap entry Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 045/159] x86/entry/64: De-Xen-ify our NMI code Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 046/159] x86/entry/32: Pull the MSR_IA32_SYSENTER_CS update code out of native_load_sp0() Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 047/159] x86/entry/64: Pass SP0 directly to load_sp0() Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 048/159] x86/entry: Add task_top_of_stack() to find the top of a tasks stack Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 049/159] x86/xen/64, x86/entry/64: Clean up SP code in cpu_initialize_context() Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 050/159] x86/entry/64: Stop initializing TSS.sp0 at boot Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 051/159] x86/entry/64: Remove all remaining direct thread_struct::sp0 reads Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 052/159] x86/entry/32: Fix cpu_current_top_of_stack initialization at boot Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 053/159] x86/entry/64: Remove thread_struct::sp0 Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 054/159] x86/traps: Use a new on_thread_stack() helper to clean up an assertion Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 055/159] x86/entry/64: Shorten TEST instructions Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 056/159] x86/cpuid: Replace set/clear_bit32() Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 057/159] bitops: Revert cbe96375025e ("bitops: Add clear/set_bit32() to linux/bitops.h") Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 058/159] x86/mm: Define _PAGE_TABLE using _KERNPG_TABLE Greg Kroah-Hartman
2017-12-22 8:45 ` Greg Kroah-Hartman [this message]
2017-12-22 8:45 ` [PATCH 4.14 060/159] x86/cpufeatures: Fix various details in the feature definitions Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 061/159] selftests/x86/ldt_gdt: Add infrastructure to test set_thread_area() Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 062/159] selftests/x86/ldt_gdt: Run most existing LDT test cases against the GDT as well Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 063/159] ACPI / APEI: Replace ioremap_page_range() with fixmap Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 064/159] x86/virt, x86/platform: Merge struct x86_hyper into struct x86_platform and struct x86_init Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 065/159] x86/virt: Add enum for hypervisors to replace x86_hyper Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 066/159] drivers/misc/intel/pti: Rename the header file to free up the namespace Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 067/159] x86/cpufeature: Add User-Mode Instruction Prevention definitions Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 068/159] x86: Make X86_BUG_FXSAVE_LEAK detectable in CPUID on AMD Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 069/159] perf/x86: Enable free running PEBS for REGS_USER/INTR Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 070/159] bpf: fix build issues on um due to mising bpf_perf_event.h Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 071/159] locking/barriers: Add implicit smp_read_barrier_depends() to READ_ONCE() Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 072/159] locking/barriers: Convert users of lockless_dereference() " Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 073/159] x86/mm/kasan: Dont use vmemmap_populate() to initialize shadow Greg Kroah-Hartman
2017-12-22 8:45 ` [PATCH 4.14 074/159] x86/entry/64/paravirt: Use paravirt-safe macro to access eflags Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 075/159] x86/unwinder/orc: Dont bail on stack overflow Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 076/159] x86/unwinder: Handle stack overflows more gracefully Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 077/159] x86/irq: Remove an old outdated comment about context tracking races Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 078/159] x86/irq/64: Print the offending IP in the stack overflow warning Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 079/159] x86/entry/64: Allocate and enable the SYSENTER stack Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 080/159] x86/dumpstack: Add get_stack_info() support for " Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 081/159] x86/entry/gdt: Put per-CPU GDT remaps in ascending order Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 082/159] x86/mm/fixmap: Generalize the GDT fixmap mechanism, introduce struct cpu_entry_area Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 083/159] x86/kasan/64: Teach KASAN about the cpu_entry_area Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 084/159] x86/entry: Fix assumptions that the HW TSS is at the beginning of cpu_tss Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 085/159] x86/dumpstack: Handle stack overflow on all stacks Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 086/159] x86/entry: Move SYSENTER_stack to the beginning of struct tss_struct Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 087/159] x86/entry: Remap the TSS into the CPU entry area Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 088/159] x86/entry/64: Separate cpu_current_top_of_stack from TSS.sp0 Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 089/159] x86/espfix/64: Stop assuming that pt_regs is on the entry stack Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 090/159] x86/entry/64: Use a per-CPU trampoline stack for IDT entries Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 091/159] x86/entry/64: Return to userspace from the trampoline stack Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 092/159] x86/entry/64: Create a per-CPU SYSCALL entry trampoline Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 093/159] x86/entry/64: Move the IST stacks into struct cpu_entry_area Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 094/159] x86/entry/64: Remove the SYSENTER stack canary Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 095/159] x86/entry: Clean up the SYSENTER_stack code Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 096/159] x86/entry/64: Make cpu_entry_area.tss read-only Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 097/159] x86/paravirt: Dont patch flush_tlb_single Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 098/159] x86/paravirt: Provide a way to check for hypervisors Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 099/159] x86/cpufeatures: Make CPU bugs sticky Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 100/159] optee: fix invalid of_node_put() in optee_driver_init() Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 101/159] backlight: pwm_bl: Fix overflow condition Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 102/159] drm: Add retries for lspcon mode detection Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 103/159] clk: sunxi-ng: nm: Check if requested rate is supported by fractional clock Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 104/159] clk: sunxi-ng: sun5i: Fix bit offset of audio PLL post-divider Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 105/159] crypto: crypto4xx - increase context and scatter ring buffer elements Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 106/159] crypto: lrw - Fix an error handling path in create() Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 107/159] rtc: pl031: make interrupt optional Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 108/159] kvm, mm: account kvm related kmem slabs to kmemcg Greg Kroah-Hartman
2017-12-22 9:34 ` Michal Hocko
2017-12-22 12:41 ` Greg Kroah-Hartman
2017-12-22 13:06 ` Michal Hocko
2017-12-22 17:40 ` alexander.levin
2017-12-22 17:56 ` Michal Hocko
2017-12-22 18:07 ` alexander.levin
2017-12-22 18:22 ` Michal Hocko
2017-12-22 21:55 ` alexander.levin
2017-12-23 9:24 ` Greg Kroah-Hartman
2017-12-27 10:30 ` Paolo Bonzini
2017-12-22 8:46 ` [PATCH 4.14 109/159] net: phy: at803x: Change error to EINVAL for invalid MAC Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 110/159] PCI: Avoid bus reset if bridge itself is broken Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 111/159] scsi: cxgb4i: fix Tx skb leak Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 112/159] scsi: mpt3sas: Fix IO error occurs on pulling out a drive from RAID1 volume created on two SATA drive Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 113/159] PCI: Create SR-IOV virtfn/physfn links before attaching driver Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 114/159] PM / OPP: Move error message to debug level Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 115/159] igb: check memory allocation failure Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 116/159] i40e: use the safe hash table iterator when deleting mac filters Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 117/159] iio: st_sensors: add register mask for status register Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 118/159] ixgbe: fix use of uninitialized padding Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 119/159] IB/rxe: check for allocation failure on elem Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 120/159] block,bfq: Disable writeback throttling Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 121/159] md: always set THREAD_WAKEUP and wake up wqueue if thread existed Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 122/159] ip_gre: check packet length and mtu correctly in erspan tx Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 123/159] ipv6: grab rt->rt6i_ref before allocating pcpu rt Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 125/159] Bluetooth: hci_uart_set_flow_control: Fix NULL deref when using serdev Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 126/159] Bluetooth: hci_bcm: Fix setting of irq trigger type Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 127/159] i40e/i40evf: spread CPU affinity hints across online CPUs only Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 128/159] PCI/AER: Report non-fatal errors only to the affected endpoint Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 129/159] tracing: Exclude generic fields from histograms Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 131/159] ASoC: img-parallel-out: Add pm_runtime_get/put to set_fmt callback Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 132/159] powerpc/xmon: Avoid tripping SMP hardlockup watchdog Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 133/159] powerpc/watchdog: Do not trigger SMP crash from touch_nmi_watchdog Greg Kroah-Hartman
2017-12-22 8:46 ` [PATCH 4.14 134/159] sctp: silence warns on sctp_stream_init allocations Greg Kroah-Hartman
2017-12-22 8:47 ` [PATCH 4.14 135/159] ASoC: codecs: msm8916-wcd-analog: fix module autoload Greg Kroah-Hartman
2017-12-22 8:47 ` [PATCH 4.14 136/159] fm10k: fix mis-ordered parameters in declaration for .ndo_set_vf_bw Greg Kroah-Hartman
2017-12-22 8:47 ` [PATCH 4.14 137/159] scsi: lpfc: Fix secure firmware updates Greg Kroah-Hartman
2017-12-22 8:47 ` [PATCH 4.14 138/159] scsi: lpfc: PLOGI failures during NPIV testing Greg Kroah-Hartman
2017-12-22 8:47 ` [PATCH 4.14 139/159] scsi: lpfc: Fix warning messages when NVME_TARGET_FC not defined Greg Kroah-Hartman
2017-12-22 8:47 ` [PATCH 4.14 140/159] i40e: fix client notify of VF reset Greg Kroah-Hartman
2017-12-22 8:47 ` [PATCH 4.14 141/159] vfio/pci: Virtualize Maximum Payload Size Greg Kroah-Hartman
2017-12-22 8:47 ` [PATCH 4.14 142/159] ARM: exynos_defconfig: Enable UAS support for Odroid HC1 board Greg Kroah-Hartman
2017-12-22 8:47 ` [PATCH 4.14 143/159] fm10k: ensure we process SM mbx when processing VF mbx Greg Kroah-Hartman
2017-12-22 8:47 ` [PATCH 4.14 144/159] ibmvnic: Set state UP Greg Kroah-Hartman
2017-12-22 8:47 ` [PATCH 4.14 145/159] net: ipv6: send NS for DAD when link operationally up Greg Kroah-Hartman
2017-12-22 8:47 ` [PATCH 4.14 146/159] RDMA/hns: Avoid NULL pointer exception Greg Kroah-Hartman
2017-12-22 8:47 ` [PATCH 4.14 147/159] staging: greybus: light: Release memory obtained by kasprintf Greg Kroah-Hartman
2017-12-22 8:47 ` [PATCH 4.14 148/159] clk: sunxi-ng: sun6i: Rename HDMI DDC clock to avoid name collision Greg Kroah-Hartman
2017-12-22 8:47 ` [PATCH 4.14 149/159] tcp: fix under-evaluated ssthresh in TCP Vegas Greg Kroah-Hartman
2017-12-22 8:47 ` [PATCH 4.14 150/159] rtc: set the alarm to the next expiring timer Greg Kroah-Hartman
2017-12-22 8:47 ` [PATCH 4.14 151/159] cpuidle: fix broadcast control when broadcast can not be entered Greg Kroah-Hartman
2017-12-22 8:47 ` [PATCH 4.14 152/159] drm/vc4: Avoid using vrefresh==0 mode in DSI htotal math Greg Kroah-Hartman
2017-12-22 8:47 ` [PATCH 4.14 153/159] IB/opa_vnic: Properly clear Mac Table Digest Greg Kroah-Hartman
2017-12-22 8:47 ` [PATCH 4.14 154/159] IB/opa_vnic: Properly return the total MACs in UC MAC list Greg Kroah-Hartman
2017-12-22 8:47 ` [PATCH 4.14 155/159] thermal/drivers/hisi: Fix missing interrupt enablement Greg Kroah-Hartman
2017-12-22 8:47 ` [PATCH 4.14 156/159] thermal/drivers/hisi: Fix kernel panic on alarm interrupt Greg Kroah-Hartman
2017-12-22 8:47 ` [PATCH 4.14 157/159] thermal/drivers/hisi: Simplify the temperature/step computation Greg Kroah-Hartman
2017-12-22 8:47 ` [PATCH 4.14 158/159] thermal/drivers/hisi: Fix multiple alarm interrupts firing Greg Kroah-Hartman
2017-12-22 8:47 ` [PATCH 4.14 159/159] platform/x86: asus-wireless: send an EV_SYN/SYN_REPORT between state changes Greg Kroah-Hartman
2017-12-22 15:08 ` [PATCH 4.14 000/159] 4.14.9-stable review Greg Kroah-Hartman
2017-12-22 15:54 ` Greg Kroah-Hartman
2017-12-22 18:15 ` Guenter Roeck
2017-12-23 14:21 ` Greg Kroah-Hartman
2017-12-23 17:09 ` Guenter Roeck
[not found] ` <5a3cfea4.0692500a.66bcf.cf6b@mx.google.com>
2017-12-22 15:11 ` Greg Kroah-Hartman
2017-12-22 15:45 ` Greg Kroah-Hartman
2017-12-22 21:09 ` Shuah Khan
2017-12-23 9:14 ` Greg Kroah-Hartman
2017-12-22 22:31 ` Dan Rue
2017-12-23 9:17 ` Greg Kroah-Hartman
2017-12-23 22:54 ` Guenter Roeck
2017-12-25 13:35 ` Greg Kroah-Hartman
2017-12-24 19:37 ` Ivan Kozik
2017-12-25 13:38 ` Greg Kroah-Hartman
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