From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga09.intel.com ([134.134.136.24]:52554 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752493AbeAERtP (ORCPT ); Fri, 5 Jan 2018 12:49:15 -0500 Date: Fri, 5 Jan 2018 09:49:13 -0800 From: Rodrigo Vivi To: Kenneth Graunke Cc: intel-gfx@lists.freedesktop.org, chris@chris-wilson.co.uk, mark.a.janes@intel.com, stable@vger.kernel.org Subject: Re: [PATCH v2] drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake. Message-ID: <20180105174913.t4mwhrcd5k5iazca@intel.com> References: <20180105085905.9298-1-kenneth@whitecape.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20180105085905.9298-1-kenneth@whitecape.org> Sender: stable-owner@vger.kernel.org List-ID: On Fri, Jan 05, 2018 at 08:59:05AM +0000, Kenneth Graunke wrote: > Geminilake requires the 3D driver to select whether barriers are > intended for compute shaders, or tessellation control shaders, by > whacking a "Barrier Mode" bit in SLICE_COMMON_ECO_CHICKEN1 when > switching pipelines. Failure to do this properly can result in GPU > hangs. > > Unfortunately, this means it needs to switch mid-batch, so only > userspace can properly set it. To facilitate this, the kernel needs > to whitelist the register. > > The workarounds page currently tags this as applying to Broxton only, > but that doesn't make sense. The documentation for the register it > references says the bit userspace is supposed to toggle only exists on > Geminilake. Empirically, the Mesa patch to toggle this bit appears to > fix intermittent GPU hangs in tessellation control shader barrier tests > on Geminilake; we haven't seen those hangs on Broxton. I just read the bit definition and fully agree with this. > > v2: Mention WA #0862 in the comment (it doesn't have a name). > > Signed-off-by: Kenneth Graunke > Acked-by: Rodrigo Vivi > Cc: stable@vger.kernel.org Merged, thanks. > --- > drivers/gpu/drm/i915/i915_reg.h | 2 ++ > drivers/gpu/drm/i915/intel_engine_cs.c | 5 +++++ > 2 files changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 966e4df9700e..505c605eff98 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -7079,6 +7079,8 @@ enum { > #define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308) > #define DISABLE_PIXEL_MASK_CAMMING (1<<14) > > +#define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c) > + > #define GEN7_L3SQCREG1 _MMIO(0xB010) > #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000 > > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c > index ebdcbcbacb3c..6bb51a502b8b 100644 > --- a/drivers/gpu/drm/i915/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c > @@ -1338,6 +1338,11 @@ static int glk_init_workarounds(struct intel_engine_cs *engine) > if (ret) > return ret; > > + /* WA #0862: Userspace has to set "Barrier Mode" to avoid hangs. */ > + ret = wa_ring_whitelist_reg(engine, GEN9_SLICE_COMMON_ECO_CHICKEN1); > + if (ret) > + return ret; > + > /* WaToEnableHwFixForPushConstHWBug:glk */ > WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, > GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); > -- > 2.15.1 >