From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-by2nam01on0100.outbound.protection.outlook.com ([104.47.34.100]:31312 "EHLO NAM01-BY2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754848AbeARVBR (ORCPT ); Thu, 18 Jan 2018 16:01:17 -0500 From: Sasha Levin To: "stable@vger.kernel.org" , "stable-commits@vger.kernel.org" CC: Sumit Semwal , Bjorn Helgaas , Sasha Levin Subject: [added to the 4.1 stable tree] PCI: Decouple IORESOURCE_ROM_ENABLE and PCI_ROM_ADDRESS_ENABLE Date: Thu, 18 Jan 2018 21:00:03 +0000 Message-ID: <20180118205908.3220-76-alexander.levin@microsoft.com> References: <20180118205908.3220-1-alexander.levin@microsoft.com> In-Reply-To: <20180118205908.3220-1-alexander.levin@microsoft.com> Content-Language: en-US Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org List-ID: From: Sumit Semwal This patch has been added to the stable tree. If you have any objections, please let us know. =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D [ Upstream commit 7a6d312b50e63f598f5b5914c4fd21878ac2b595 ] Remove the assumption that IORESOURCE_ROM_ENABLE =3D=3D PCI_ROM_ADDRESS_ENA= BLE. PCI_ROM_ADDRESS_ENABLE is the ROM enable bit defined by the PCI spec, so if we're reading or writing a BAR register value, that's what we should use. IORESOURCE_ROM_ENABLE is a corresponding bit in struct resource flags. Signed-off-by: Bjorn Helgaas Reviewed-by: Gavin Shan Signed-off-by: Sasha Levin --- drivers/pci/probe.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 5754d7b48c1f..c7dc06636bf6 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -223,7 +223,8 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_t= ype type, mask64 =3D (u32)PCI_BASE_ADDRESS_MEM_MASK; } } else { - res->flags |=3D (l & IORESOURCE_ROM_ENABLE); + if (l & PCI_ROM_ADDRESS_ENABLE) + res->flags |=3D IORESOURCE_ROM_ENABLE; l64 =3D l & PCI_ROM_ADDRESS_MASK; sz64 =3D sz & PCI_ROM_ADDRESS_MASK; mask64 =3D (u32)PCI_ROM_ADDRESS_MASK; --=20 2.11.0