From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: From: Sasha Levin To: "linux-kernel@vger.kernel.org" , "stable@vger.kernel.org" CC: Laxman Dewangan , Thierry Reding , Sasha Levin Subject: [PATCH AUTOSEL for 4.4 009/101] pwm: tegra: Increase precision in PWM rate calculation Date: Thu, 8 Mar 2018 05:01:12 +0000 Message-ID: <20180308050023.8548-9-alexander.levin@microsoft.com> References: <20180308050023.8548-1-alexander.levin@microsoft.com> In-Reply-To: <20180308050023.8548-1-alexander.levin@microsoft.com> Content-Language: en-US Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: From: Laxman Dewangan [ Upstream commit 250b76f43f57d578ebff5e7211eb2c73aa5cd6ca ] The rate of the PWM calculated as follows: hz =3D NSEC_PER_SEC / period_ns; rate =3D (rate + (hz / 2)) / hz; This has the precision loss in lower PWM rate. Change this to have more precision as: hz =3D DIV_ROUND_CLOSEST_ULL(NSEC_PER_SEC * 100, period_ns); rate =3D DIV_ROUND_CLOSEST(rate * 100, hz) Example: 1. period_ns =3D 16672000, PWM clock rate is 200 KHz. Based on old formula hz =3D NSEC_PER_SEC / period_ns =3D 1000000000ul/16672000 =3D 59 (59.98) rate =3D (200K + 59/2)/59 =3D 3390 Based on new method: hz =3D 5998 rate =3D DIV_ROUND_CLOSE(200000*100, 5998) =3D 3334 If we measure the PWM signal rate, we will get more accurate period with rate value of 3334 instead of 3390. 2. period_ns =3D 16803898, PWM clock rate is 200 KHz. Based on old formula: hz =3D 59, rate =3D 3390 Based on new formula: hz =3D 5951, rate =3D 3360 The PWM signal rate of 3360 is more near to requested period than 3333. Signed-off-by: Laxman Dewangan Signed-off-by: Thierry Reding Signed-off-by: Sasha Levin --- drivers/pwm/pwm-tegra.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c index d4de0607b502..3039fb762893 100644 --- a/drivers/pwm/pwm-tegra.c +++ b/drivers/pwm/pwm-tegra.c @@ -69,6 +69,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct= pwm_device *pwm, struct tegra_pwm_chip *pc =3D to_tegra_pwm_chip(chip); unsigned long long c; unsigned long rate, hz; + unsigned long long ns100 =3D NSEC_PER_SEC; u32 val =3D 0; int err; =20 @@ -87,9 +88,11 @@ static int tegra_pwm_config(struct pwm_chip *chip, struc= t pwm_device *pwm, * cycles at the PWM clock rate will take period_ns nanoseconds. */ rate =3D clk_get_rate(pc->clk) >> PWM_DUTY_WIDTH; - hz =3D NSEC_PER_SEC / period_ns; =20 - rate =3D (rate + (hz / 2)) / hz; + /* Consider precision in PWM_SCALE_WIDTH rate calculation */ + ns100 *=3D 100; + hz =3D DIV_ROUND_CLOSEST_ULL(ns100, period_ns); + rate =3D DIV_ROUND_CLOSEST(rate * 100, hz); =20 /* * Since the actual PWM divider is the register's frequency divider --=20 2.14.1