From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-cys01nam02on0101.outbound.protection.outlook.com ([104.47.37.101]:53605 "EHLO NAM02-CY1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S966885AbeCSQN6 (ORCPT ); Mon, 19 Mar 2018 12:13:58 -0400 From: Sasha Levin To: "linux-kernel@vger.kernel.org" , "stable@vger.kernel.org" CC: Thomas Bogendoerfer , Greg Kroah-Hartman , Sasha Levin Subject: [PATCH AUTOSEL for 3.18 067/102] Fix serial console on SNI RM400 machines Date: Mon, 19 Mar 2018 16:12:52 +0000 Message-ID: <20180319161117.17833-67-alexander.levin@microsoft.com> References: <20180319161117.17833-1-alexander.levin@microsoft.com> In-Reply-To: <20180319161117.17833-1-alexander.levin@microsoft.com> Content-Language: en-US Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org List-ID: From: Thomas Bogendoerfer [ Upstream commit e279e6d98e0cf2c2fe008b3c29042b92f0e17b1d ] sccnxp driver doesn't get the correct uart clock rate, if CONFIG_HAVE_CLOCK is disabled. Correct usage of clk API to make it work with/without it. Fixes: 90efa75f7ab0 (serial: sccnxp: Using CLK API for getting UART clock) Suggested-by: Russell King - ARM Linux Signed-off-by: Thomas Bogendoerfer Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/tty/serial/sccnxp.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/tty/serial/sccnxp.c b/drivers/tty/serial/sccnxp.c index 75850f70b479..72f4146e8eed 100644 --- a/drivers/tty/serial/sccnxp.c +++ b/drivers/tty/serial/sccnxp.c @@ -884,14 +884,19 @@ static int sccnxp_probe(struct platform_device *pdev) =20 clk =3D devm_clk_get(&pdev->dev, NULL); if (IS_ERR(clk)) { - if (PTR_ERR(clk) =3D=3D -EPROBE_DEFER) { - ret =3D -EPROBE_DEFER; + ret =3D PTR_ERR(clk); + if (ret =3D=3D -EPROBE_DEFER) goto err_out; - } + uartclk =3D 0; + } else { + clk_prepare_enable(clk); + uartclk =3D clk_get_rate(clk); + } + + if (!uartclk) { dev_notice(&pdev->dev, "Using default clock frequency\n"); uartclk =3D s->chip->freq_std; - } else - uartclk =3D clk_get_rate(clk); + } =20 /* Check input frequency */ if ((uartclk < s->chip->freq_min) || (uartclk > s->chip->freq_max)) { --=20 2.14.1