From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: From: Sasha Levin To: "stable@vger.kernel.org" , "linux-kernel@vger.kernel.org" CC: Maarten ter Huurne , Ralf Baechle , "linux-mips@linux-mips.org" , James Hogan , Sasha Levin Subject: [PATCH AUTOSEL for 4.15 049/189] MIPS: JZ4770: Work around config2 misreporting associativity Date: Mon, 9 Apr 2018 00:17:24 +0000 Message-ID: <20180409001637.162453-49-alexander.levin@microsoft.com> References: <20180409001637.162453-1-alexander.levin@microsoft.com> In-Reply-To: <20180409001637.162453-1-alexander.levin@microsoft.com> Content-Language: en-US Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: From: Maarten ter Huurne [ Upstream commit 1f7412e0e2f327fe7dc5a0c2fc36d7b319d05d47 ] According to config2, the associativity would be 5-ways, but the documentation states 4-ways, which also matches the documented L2 cache size of 256 kB. Signed-off-by: Maarten ter Huurne Reviewed-by: James Hogan Cc: Ralf Baechle Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18488/ Signed-off-by: James Hogan Signed-off-by: Sasha Levin --- arch/mips/mm/sc-mips.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c index 548acb7f8557..394673991bab 100644 --- a/arch/mips/mm/sc-mips.c +++ b/arch/mips/mm/sc-mips.c @@ -16,6 +16,7 @@ #include #include #include +#include =20 /* * MIPS32/MIPS64 L2 cache handling @@ -220,6 +221,14 @@ static inline int __init mips_sc_probe(void) else return 0; =20 + /* + * According to config2 it would be 5-ways, but that is contradicted + * by all documentation. + */ + if (current_cpu_type() =3D=3D CPU_JZRISC && + mips_machtype =3D=3D MACH_INGENIC_JZ4770) + c->scache.ways =3D 4; + c->scache.waysize =3D c->scache.sets * c->scache.linesz; c->scache.waybit =3D __ffs(c->scache.waysize); =20 --=20 2.15.1