From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.kernel.org ([198.145.29.99]:54148 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1031491AbeEXKEw (ORCPT ); Thu, 24 May 2018 06:04:52 -0400 From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Yixun Lan , Jerome Brunet , Sasha Levin Subject: [PATCH 4.16 132/161] clk: meson: axg: fix the od shift of the sys_pll Date: Thu, 24 May 2018 11:39:17 +0200 Message-Id: <20180524093034.156085563@linuxfoundation.org> In-Reply-To: <20180524093018.331893860@linuxfoundation.org> References: <20180524093018.331893860@linuxfoundation.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Sender: stable-owner@vger.kernel.org List-ID: 4.16-stable review patch. If anyone has any objections, please let me know. ------------------ From: Yixun Lan [ Upstream commit 2fa9b361e500a0e092a9525afbd6a3a363ffa5f0 ] According to the datasheet, the od shift of sys_pll is actually 16. Fixes: 78b4af312f91 ('clk: meson-axg: add clock controller drivers') Signed-off-by: Yixun Lan [fixed commit message] Signed-off-by: Jerome Brunet Signed-off-by: Sasha Levin Signed-off-by: Greg Kroah-Hartman --- drivers/clk/meson/axg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -151,7 +151,7 @@ static struct meson_clk_pll axg_sys_pll }, .od = { .reg_off = HHI_SYS_PLL_CNTL, - .shift = 10, + .shift = 16, .width = 2, }, .rate_table = sys_pll_rate_table,