From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.bootlin.com ([62.4.15.54]:38508 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932860AbeFROGc (ORCPT ); Mon, 18 Jun 2018 10:06:32 -0400 Date: Mon, 18 Jun 2018 16:06:30 +0200 From: Miquel Raynal To: Martin Kaiser Cc: Boris Brezillon , David Woodhouse , Sascha Hauer , Fabio Estevam , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: Re: [PATCH v2] mtd: rawnand: mxc: set spare area size register explicitly Message-ID: <20180618160630.261404f8@xps13> In-Reply-To: <1528637487-25172-1-git-send-email-martin@kaiser.cx> References: <1528025495-14443-1-git-send-email-martin@kaiser.cx> <1528637487-25172-1-git-send-email-martin@kaiser.cx> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Sender: stable-owner@vger.kernel.org List-ID: Hi Martin, On Sun, 10 Jun 2018 15:31:27 +0200, Martin Kaiser wrote: > The v21 version of the NAND flash controller contains a Spare Area Size > Register (SPAS) at offset 0x10. Its setting defaults to the maximum > spare area size of 218 bytes. The size that is set in this register is > used by the controller when it calculates the ECC bytes internally in > hardware. > > Usually, this register is updated from settings in the IIM fuses when > the system is booting from NAND flash. For other boot media, however, > the SPAS register remains at the default setting, which may not work for > the particular flash chip on the board. The same goes for flash chips > whose configuration cannot be set in the IIM fuses (e.g. chips with 2k > sector size and 128 bytes spare area size can't be configured in the IIM > fuses on imx25 systems). > > Set the SPAS register explicitly during the preset operation. Derive the > register value from mtd->oobsize that was detected during probe by > decoding the flash chip's ID bytes. > > While at it, rename the define for the spare area register's offset to > NFC_V21_RSLTSPARE_AREA. The register at offset 0x10 on v1 controllers is > different from the register on v21 controllers. > > Signed-off-by: Martin Kaiser > Reviewed-by: Sascha Hauer > Cc: stable@vger.kernel.org > --- Thanks, I'm ok with the patch, I'll queue it to nand/next. > changes in v2 > - fix the commit message > - use '/ 2' instead of shift operator for division > > BTW is it ok to keep a Reviewed-by tag when updating the patch? I think so, at least for such minor updates it is okay :) Regards, Miquèl