From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-cys01nam02on0091.outbound.protection.outlook.com ([104.47.37.91]:41829 "EHLO NAM02-CY1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727487AbeIBRTz (ORCPT ); Sun, 2 Sep 2018 13:19:55 -0400 From: Sasha Levin To: "stable@vger.kernel.org" , "linux-kernel@vger.kernel.org" CC: Amit Daniel Kachhap , Stephen Boyd , Sasha Levin Subject: [PATCH AUTOSEL 4.18 019/131] clk: scmi: Fix the rounding of clock rate Date: Sun, 2 Sep 2018 13:03:22 +0000 Message-ID: <20180902064601.183036-19-alexander.levin@microsoft.com> References: <20180902064601.183036-1-alexander.levin@microsoft.com> In-Reply-To: <20180902064601.183036-1-alexander.levin@microsoft.com> Content-Language: en-US Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org List-ID: From: Amit Daniel Kachhap [ Upstream commit 7a8655e19bdb3be43f6a3b4768c9b0928a2585fc ] This fix rounds the clock rate properly by using quotient and not remainder in the calculation. This issue was found while testing HDMI in the Juno platform. Fixes: 6d6a1d82eaef7 ("clk: add support for clocks provided by SCMI") Acked-by: Sudeep Holla Signed-off-by: Amit Daniel Kachhap Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin --- drivers/clk/clk-scmi.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-scmi.c b/drivers/clk/clk-scmi.c index bb2a6f2f5516..a985bf5e1ac6 100644 --- a/drivers/clk/clk-scmi.c +++ b/drivers/clk/clk-scmi.c @@ -38,7 +38,6 @@ static unsigned long scmi_clk_recalc_rate(struct clk_hw *= hw, static long scmi_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { - int step; u64 fmin, fmax, ftmp; struct scmi_clk *clk =3D to_scmi_clk(hw); =20 @@ -60,9 +59,9 @@ static long scmi_clk_round_rate(struct clk_hw *hw, unsign= ed long rate, =20 ftmp =3D rate - fmin; ftmp +=3D clk->info->range.step_size - 1; /* to round up */ - step =3D do_div(ftmp, clk->info->range.step_size); + do_div(ftmp, clk->info->range.step_size); =20 - return step * clk->info->range.step_size + fmin; + return ftmp * clk->info->range.step_size + fmin; } =20 static int scmi_clk_set_rate(struct clk_hw *hw, unsigned long rate, --=20 2.17.1