From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-eopbgr680117.outbound.protection.outlook.com ([40.107.68.117]:50363 "EHLO NAM04-BN3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728245AbeIBRUq (ORCPT ); Sun, 2 Sep 2018 13:20:46 -0400 From: Sasha Levin To: "stable@vger.kernel.org" , "linux-kernel@vger.kernel.org" CC: Daniel Mack , Linus Walleij , Sasha Levin Subject: [PATCH AUTOSEL 4.18 077/131] gpio: pxa: disable pinctrl calls for PXA3xx Date: Sun, 2 Sep 2018 13:04:42 +0000 Message-ID: <20180902064601.183036-77-alexander.levin@microsoft.com> References: <20180902064601.183036-1-alexander.levin@microsoft.com> In-Reply-To: <20180902064601.183036-1-alexander.levin@microsoft.com> Content-Language: en-US Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org List-ID: From: Daniel Mack [ Upstream commit 9dabfdd84bdfa25f0df486dd3de43e53e79a1892 ] The pxa3xx driver uses the pinctrl-single driver since a while which does not implement a .gpio_set_direction() callback. The pinmux core will simply return 0 in this case, and the pxa3xx gpio driver hence believes the pinctrl driver did its job and returns as well. This effectively makes pxa_gpio_direction_{input,output} no-ops. To fix this, do not call into the pinctrl subsystem for the PXA3xx platform for now. We can revert this once the pinctrl-single driver learned to support setting pin directions. Signed-off-by: Daniel Mack Acked-by: Robert Jarzmik Signed-off-by: Linus Walleij Signed-off-by: Sasha Levin --- drivers/gpio/gpio-pxa.c | 35 +++++++++++++++++++++++++++-------- 1 file changed, 27 insertions(+), 8 deletions(-) diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c index 1e66f808051c..2e33fd552899 100644 --- a/drivers/gpio/gpio-pxa.c +++ b/drivers/gpio/gpio-pxa.c @@ -241,6 +241,17 @@ int pxa_irq_to_gpio(int irq) return irq_gpio0; } =20 +static bool pxa_gpio_has_pinctrl(void) +{ + switch (gpio_type) { + case PXA3XX_GPIO: + return false; + + default: + return true; + } +} + static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset) { struct pxa_gpio_chip *pchip =3D chip_to_pxachip(chip); @@ -255,9 +266,11 @@ static int pxa_gpio_direction_input(struct gpio_chip *= chip, unsigned offset) unsigned long flags; int ret; =20 - ret =3D pinctrl_gpio_direction_input(chip->base + offset); - if (!ret) - return 0; + if (pxa_gpio_has_pinctrl()) { + ret =3D pinctrl_gpio_direction_input(chip->base + offset); + if (!ret) + return 0; + } =20 spin_lock_irqsave(&gpio_lock, flags); =20 @@ -282,9 +295,11 @@ static int pxa_gpio_direction_output(struct gpio_chip = *chip, =20 writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET)); =20 - ret =3D pinctrl_gpio_direction_output(chip->base + offset); - if (ret) - return ret; + if (pxa_gpio_has_pinctrl()) { + ret =3D pinctrl_gpio_direction_output(chip->base + offset); + if (ret) + return ret; + } =20 spin_lock_irqsave(&gpio_lock, flags); =20 @@ -348,8 +363,12 @@ static int pxa_init_gpio_chip(struct pxa_gpio_chip *pc= hip, int ngpio, pchip->chip.set =3D pxa_gpio_set; pchip->chip.to_irq =3D pxa_gpio_to_irq; pchip->chip.ngpio =3D ngpio; - pchip->chip.request =3D gpiochip_generic_request; - pchip->chip.free =3D gpiochip_generic_free; + + if (pxa_gpio_has_pinctrl()) { + pchip->chip.request =3D gpiochip_generic_request; + pchip->chip.free =3D gpiochip_generic_free; + } + #ifdef CONFIG_OF_GPIO pchip->chip.of_node =3D np; pchip->chip.of_xlate =3D pxa_gpio_of_xlate; --=20 2.17.1