From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-eopbgr730103.outbound.protection.outlook.com ([40.107.73.103]:49315 "EHLO NAM05-DM3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728273AbeIOGrL (ORCPT ); Sat, 15 Sep 2018 02:47:11 -0400 From: Sasha Levin To: "stable@vger.kernel.org" , "linux-kernel@vger.kernel.org" CC: Ryder Lee , Matthias Brugger , Sasha Levin Subject: [PATCH AUTOSEL 4.18 22/92] arm64: dts: mt7622: update a clock property for UART0 Date: Sat, 15 Sep 2018 01:30:04 +0000 Message-ID: <20180915012944.179481-22-alexander.levin@microsoft.com> References: <20180915012944.179481-1-alexander.levin@microsoft.com> In-Reply-To: <20180915012944.179481-1-alexander.levin@microsoft.com> Content-Language: en-US Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org List-ID: From: Ryder Lee [ Upstream commit 2b519747ae4859e886c37834d766fe0c7d8d82e2 ] The input clock of UART0 should be CLK_PERI_UART0_PD. Fixes: 13f36c326cef ("arm64: dts: mt7622: turn uart0 clock to real ones") Signed-off-by: Ryder Lee Signed-off-by: Matthias Brugger Signed-off-by: Sasha Levin --- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts= /mediatek/mt7622.dtsi index 9213c966c224..ec7ea8dca777 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi @@ -331,7 +331,7 @@ reg =3D <0 0x11002000 0 0x400>; interrupts =3D ; clocks =3D <&topckgen CLK_TOP_UART_SEL>, - <&pericfg CLK_PERI_UART1_PD>; + <&pericfg CLK_PERI_UART0_PD>; clock-names =3D "baud", "bus"; status =3D "disabled"; }; --=20 2.17.1