From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-eopbgr720090.outbound.protection.outlook.com ([40.107.72.90]:59680 "EHLO NAM05-CO1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728347AbeIOGsv (ORCPT ); Sat, 15 Sep 2018 02:48:51 -0400 From: Sasha Levin To: "stable@vger.kernel.org" , "linux-kernel@vger.kernel.org" CC: Harry Wentland , Alex Deucher , Sasha Levin Subject: [PATCH AUTOSEL 4.18 79/92] drm/amd/pp: Send khz clock values to DC for smu7/8 Date: Sat, 15 Sep 2018 01:30:46 +0000 Message-ID: <20180915012944.179481-78-alexander.levin@microsoft.com> References: <20180915012944.179481-1-alexander.levin@microsoft.com> In-Reply-To: <20180915012944.179481-1-alexander.levin@microsoft.com> Content-Language: en-US Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org List-ID: From: Harry Wentland [ Upstream commit c3cb424a086921f6bb0449b10d998352a756d6d5 ] The previous change wasn't covering smu 7 and 8 and therefore DC was seeing wrong clock values. This fixes an issue where the pipes seem to hang with a 4k DP and 1080p HDMI display. Fixes: c3df50abc84b ("drm/amd/pp: Convert clock unit to KHz as defined") Signed-off-by: Harry Wentland Acked-by: Alex Deucher Cc:rex.zhu@amd.com Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 8 ++++---- drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c | 6 +++--- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu= /drm/amd/powerplay/hwmgr/smu7_hwmgr.c index f8e866ceda02..77779adeef28 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c @@ -4555,12 +4555,12 @@ static int smu7_get_sclks(struct pp_hwmgr *hwmgr, s= truct amd_pp_clocks *clocks) return -EINVAL; dep_sclk_table =3D table_info->vdd_dep_on_sclk; for (i =3D 0; i < dep_sclk_table->count; i++) - clocks->clock[i] =3D dep_sclk_table->entries[i].clk; + clocks->clock[i] =3D dep_sclk_table->entries[i].clk * 10; clocks->count =3D dep_sclk_table->count; } else if (hwmgr->pp_table_version =3D=3D PP_TABLE_V0) { sclk_table =3D hwmgr->dyn_state.vddc_dependency_on_sclk; for (i =3D 0; i < sclk_table->count; i++) - clocks->clock[i] =3D sclk_table->entries[i].clk; + clocks->clock[i] =3D sclk_table->entries[i].clk * 10; clocks->count =3D sclk_table->count; } =20 @@ -4592,7 +4592,7 @@ static int smu7_get_mclks(struct pp_hwmgr *hwmgr, str= uct amd_pp_clocks *clocks) return -EINVAL; dep_mclk_table =3D table_info->vdd_dep_on_mclk; for (i =3D 0; i < dep_mclk_table->count; i++) { - clocks->clock[i] =3D dep_mclk_table->entries[i].clk; + clocks->clock[i] =3D dep_mclk_table->entries[i].clk * 10; clocks->latency[i] =3D smu7_get_mem_latency(hwmgr, dep_mclk_table->entries[i].clk); } @@ -4600,7 +4600,7 @@ static int smu7_get_mclks(struct pp_hwmgr *hwmgr, str= uct amd_pp_clocks *clocks) } else if (hwmgr->pp_table_version =3D=3D PP_TABLE_V0) { mclk_table =3D hwmgr->dyn_state.vddc_dependency_on_mclk; for (i =3D 0; i < mclk_table->count; i++) - clocks->clock[i] =3D mclk_table->entries[i].clk; + clocks->clock[i] =3D mclk_table->entries[i].clk * 10; clocks->count =3D mclk_table->count; } return 0; diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c b/drivers/gpu= /drm/amd/powerplay/hwmgr/smu8_hwmgr.c index 50690c72b2ea..288802f209dd 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c @@ -1604,17 +1604,17 @@ static int smu8_get_clock_by_type(struct pp_hwmgr *= hwmgr, enum amd_pp_clock_type switch (type) { case amd_pp_disp_clock: for (i =3D 0; i < clocks->count; i++) - clocks->clock[i] =3D data->sys_info.display_clock[i]; + clocks->clock[i] =3D data->sys_info.display_clock[i] * 10; break; case amd_pp_sys_clock: table =3D hwmgr->dyn_state.vddc_dependency_on_sclk; for (i =3D 0; i < clocks->count; i++) - clocks->clock[i] =3D table->entries[i].clk; + clocks->clock[i] =3D table->entries[i].clk * 10; break; case amd_pp_mem_clock: clocks->count =3D SMU8_NUM_NBPMEMORYCLOCK; for (i =3D 0; i < clocks->count; i++) - clocks->clock[i] =3D data->sys_info.nbp_memory_clock[clocks->count - 1 = - i]; + clocks->clock[i] =3D data->sys_info.nbp_memory_clock[clocks->count - 1 = - i] * 10; break; default: return -1; --=20 2.17.1