From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.bootlin.com ([62.4.15.54]:43781 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730604AbeIXVRk (ORCPT ); Mon, 24 Sep 2018 17:17:40 -0400 From: Thomas Petazzoni To: stable@vger.kernel.org Cc: Zachary Zhang , Thomas Petazzoni , Lorenzo Pieralisi Subject: [PATCH stable v4.17] PCI: aardvark: Size bridges before resources allocation Date: Mon, 24 Sep 2018 17:14:50 +0200 Message-Id: <20180924151450.3184-1-thomas.petazzoni@bootlin.com> Sender: stable-owner@vger.kernel.org List-ID: From: Zachary Zhang commit 91a2968e245d6ba616db37001fa1a043078b1a65 usptream. The PCIE I/O and MEM resource allocation mechanism is that root bus goes through the following steps: 1. Check PCI bridges' range and computes I/O and Mem base/limits. 2. Sort all subordinate devices I/O and MEM resource requirements and allocate the resources and writes/updates subordinate devices' requirements to PCI bridges I/O and Mem MEM/limits registers. Currently, PCI Aardvark driver only handles the second step and lacks the first step, so there is an I/O and MEM resource allocation failure when using a PCI switch. This commit fixes that by sizing bridges before doing the resource allocation. Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver") Signed-off-by: Zachary Zhang [Thomas: edit commit log.] Signed-off-by: Thomas Petazzoni Signed-off-by: Lorenzo Pieralisi Cc: --- drivers/pci/host/pci-aardvark.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c index d0867a311f42..806fa836b2d6 100644 --- a/drivers/pci/host/pci-aardvark.c +++ b/drivers/pci/host/pci-aardvark.c @@ -951,6 +951,7 @@ static int advk_pcie_probe(struct platform_device *pdev) bus = bridge->bus; + pci_bus_size_bridges(bus); pci_bus_assign_resources(bus); list_for_each_entry(child, &bus->children, node) -- 2.14.4