From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.bootlin.com ([62.4.15.54]:44272 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726106AbeI1NTZ (ORCPT ); Fri, 28 Sep 2018 09:19:25 -0400 Date: Fri, 28 Sep 2018 08:56:56 +0200 From: Boris Brezillon To: Chris Packham Cc: "linux-mtd@lists.infradead.org" , "stable@vger.kernel.org" , Daniel Mack , Miquel Raynal Subject: Re: [PATCH v2] mtd: rawnand: marvell: check for RDY bits after enabling the IRQ Message-ID: <20180928085656.6b0be35a@bbrezillon> In-Reply-To: <20180928084046.221bdda0@bbrezillon> References: <20180927071751.21513-1-daniel@zonque.org> <20180927101145.4c2d1159@xps13> <20180927105630.19fc1ff8@bbrezillon> <20180928084046.221bdda0@bbrezillon> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: stable-owner@vger.kernel.org List-ID: On Fri, 28 Sep 2018 08:40:46 +0200 Boris Brezillon wrote: > > marvell-nfc f10d0000.nand-controller: Timeout on RDDREQ while draining > > FIFO (data) (NDSR: 0x00000810) > > ttyS ttyS1: tty_port_close_start: tty->count = 1 port count = 2 > > marvell-nfc f10d0000.nand-controller: Timeout on RDDREQ while draining > > FIFO (data) (NDSR: 0x00000810) > > marvell-nfc f10d0000.nand-controller: Timeout on RDDREQ while draining > > FIFO (data) (NDSR: 0x00000810) > > marvell-nfc f10d0000.nand-controller: Timeout on RDDREQ while draining > > FIFO (data) (NDSR: 0x00000810) > > marvell-nfc f10d0000.nand-controller: Timeout on RDDREQ while draining > > FIFO (data) (NDSR: 0x00000810) > > marvell-nfc f10d0000.nand-controller: Timeout on RDDREQ while draining > > FIFO (data) (NDSR: 0x00000810) > > marvell-nfc f10d0000.nand-controller: Timeout on RDDREQ while draining > > FIFO (data) (NDSR: 0x00000810) > > > > ... (RDDREQ messages repeat). > > Hm, that's weird, unless RDDREQ is a 'clear-on-read' bit, that > shouldn't happen. BTW, I dropped the patch.