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From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Boris Brezillon <boris.brezillon@bootlin.com>
Cc: Chris Packham <Chris.Packham@alliedtelesis.co.nz>,
	Daniel Mack <daniel@zonque.org>,
	"linux-mtd@lists.infradead.org" <linux-mtd@lists.infradead.org>,
	"stable@vger.kernel.org" <stable@vger.kernel.org>
Subject: Re: [PATCH v2] mtd: rawnand: marvell: check for RDY bits after enabling the IRQ
Date: Tue, 2 Oct 2018 09:25:00 +0200	[thread overview]
Message-ID: <20181002092500.3dc2ac7a@xps13> (raw)
In-Reply-To: <20181002084601.2a118f10@xps13>

Hi Daniel, Chris,

Miquel Raynal <miquel.raynal@bootlin.com> wrote on Tue, 2 Oct 2018
08:46:01 +0200:

> Hi Boris,
> 
> Boris Brezillon <boris.brezillon@bootlin.com> wrote on Tue, 2 Oct 2018
> 00:13:28 +0200:
> 
> > On Mon, 1 Oct 2018 22:01:27 +0000
> > Chris Packham <Chris.Packham@alliedtelesis.co.nz> wrote:
> >   
> > > On 02/10/18 10:41, Boris Brezillon wrote:    
> > > > On Mon, 1 Oct 2018 22:34:38 +0200
> > > > Boris Brezillon <boris.brezillon@bootlin.com> wrote:
> > > >          
> > > >>>
> > > >>> I'd previously tried readl() based on the same hunch. No change.
> > > >>>
> > > >>> I think my snippet above might be misleading. While a delay between
> > > >>> readl_relaxed() and the if should not change the outcome, this is also a
> > > >>> delay between marvell_nfc_enable_int() and marvell_nfc_disable_int()
> > > >>> which is probably more significant. Sure enough if I move the delay to
> > > >>> just before the marvell_nfc_disable_int() the error is not seen.      
> > > >>
> > > >> AFAICT, your timeout always happens when waiting for RDREQ, not RDYM.
> > > >> So maybe disabling MRDY too early has a side-effect on the RDREQ event.      
> > > > 
> > > > Can you try with this patch [1]? It should ensure that NDSR_RDY bits
> > > > are cleared before starting an operation.
> > > > 
> > > > [1]http://code.bulix.org/lgs30c-468205
> > > >       
> > > 
> > > No luck. I applied that on top of Daniel's and got the same result.
> > > 
> > > One thing that does look promising is the following modification of 
> > > Daniel's patch[1]. Which moves the RDY check to before where the 
> > > interrupts are enabled.    
> > 
> > Except we still don't know why this is happening, and I'm not sure I
> > want to take a fix without understanding why it does fix the problem.
> > 
> > Also, it looks like complete() is not called until the RDDREQ, WRDREQ
> > and WRCMDREQ are cleared in the interrupt handler [1], which is weird.
> > Miquel, do you happen to remember why you had to do that?  
> 
> The RDDREQ, WRDREQ and WRCMDREQ events might potentially happen while
> the interrupts are enabled while we only wait for R/B signalling. This
> check is to avoid calling complete() on these situations.

Actually Boris is right on the fact that while the intention is good,
the writing of [1] is not accurate. Daniel, could you please test if
the following diff changes something with your setup, without your
patch?


diff --git a/drivers/mtd/nand/raw/marvell_nand.c b/drivers/mtd/nand/raw/marvell_nand.c
index bc2ef5209783..c7573ccdbacd 100644
--- a/drivers/mtd/nand/raw/marvell_nand.c
+++ b/drivers/mtd/nand/raw/marvell_nand.c
@@ -686,7 +686,7 @@ static irqreturn_t marvell_nfc_isr(int irq, void *dev_id)
 
        marvell_nfc_disable_int(nfc, st & NDCR_ALL_INT);
 
-       if (!(st & (NDSR_RDDREQ | NDSR_WRDREQ | NDSR_WRCMDREQ)))
+       if (st & (NDSR_RDY(0) | NDSR_RDY(1)))
                complete(&nfc->complete);
 
        return IRQ_HANDLED;

> 
> > 
> > [1]https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/mtd/nand/raw/marvell_nand.c?h=v4.19-rc6#n689  
> 


Thanks,
Miquèl

  reply	other threads:[~2018-10-02 14:07 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-09-27  7:17 [PATCH v2] mtd: rawnand: marvell: check for RDY bits after enabling the IRQ Daniel Mack
2018-09-27  8:11 ` Miquel Raynal
2018-09-27  8:56   ` Boris Brezillon
2018-09-27 21:55     ` Chris Packham
2018-09-28  6:40       ` Boris Brezillon
2018-09-28  6:56         ` Boris Brezillon
2018-09-28  8:12         ` Miquel Raynal
2018-09-28  7:43       ` Daniel Mack
2018-09-28  8:24         ` Miquel Raynal
2018-09-28  8:29           ` Daniel Mack
2018-09-30 21:10             ` Chris Packham
2018-10-01  5:31               ` Daniel Mack
2018-10-01 19:59                 ` Chris Packham
2018-10-01 20:34                   ` Boris Brezillon
2018-10-01 21:41                     ` Boris Brezillon
2018-10-01 22:01                       ` Chris Packham
2018-10-01 22:13                         ` Boris Brezillon
2018-10-01 22:15                           ` Chris Packham
2018-10-02  9:36                             ` Boris Brezillon
2018-10-02  9:37                               ` Boris Brezillon
2018-10-02  6:46                           ` Miquel Raynal
2018-10-02  7:25                             ` Miquel Raynal [this message]
2018-10-02  8:22                               ` Daniel Mack
2018-10-02 20:53                                 ` Chris Packham
2018-10-03  7:33                                   ` Miquel Raynal
2018-10-03  7:54                                     ` Daniel Mack
2018-10-01 22:44 ` Boris Brezillon
2018-10-02  7:42   ` Daniel Mack

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