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From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Chris Packham <Chris.Packham@alliedtelesis.co.nz>
Cc: Daniel Mack <daniel@zonque.org>,
	Boris Brezillon <boris.brezillon@bootlin.com>,
	"linux-mtd@lists.infradead.org" <linux-mtd@lists.infradead.org>,
	"stable@vger.kernel.org" <stable@vger.kernel.org>
Subject: Re: [PATCH v2] mtd: rawnand: marvell: check for RDY bits after enabling the IRQ
Date: Wed, 3 Oct 2018 09:33:02 +0200	[thread overview]
Message-ID: <20181003093302.4b810e64@xps13> (raw)
In-Reply-To: <da3e196e239545cfb533a84d9ad71656@svr-chch-ex1.atlnz.lc>

Hi Chris,

Chris Packham <Chris.Packham@alliedtelesis.co.nz> wrote on Tue, 2 Oct
2018 20:53:14 +0000:

> On 02/10/18 21:23, Daniel Mack wrote:
> > Hi Miquel,
> > 
> > On 2/10/2018 9:25 AM, Miquel Raynal wrote:  
> >> Miquel Raynal <miquel.raynal@bootlin.com> wrote on Tue, 2 Oct 2018
> >> 08:46:01 +0200:  
> >>> Boris Brezillon <boris.brezillon@bootlin.com> wrote on Tue, 2 Oct 2018
> >>> 00:13:28 +0200:  
> >   
> >>>> Also, it looks like complete() is not called until the RDDREQ, WRDREQ
> >>>> and WRCMDREQ are cleared in the interrupt handler [1], which is weird.
> >>>> Miquel, do you happen to remember why you had to do that?  
> >>>
> >>> The RDDREQ, WRDREQ and WRCMDREQ events might potentially happen while
> >>> the interrupts are enabled while we only wait for R/B signalling. This
> >>> check is to avoid calling complete() on these situations.  
> >>
> >> Actually Boris is right on the fact that while the intention is good,
> >> the writing of [1] is not accurate. Daniel, could you please test if
> >> the following diff changes something with your setup, without your
> >> patch?
> >>
> >>
> >> diff --git a/drivers/mtd/nand/raw/marvell_nand.c b/drivers/mtd/nand/raw/marvell_nand.c
> >> index bc2ef5209783..c7573ccdbacd 100644
> >> --- a/drivers/mtd/nand/raw/marvell_nand.c
> >> +++ b/drivers/mtd/nand/raw/marvell_nand.c
> >> @@ -686,7 +686,7 @@ static irqreturn_t marvell_nfc_isr(int irq, void *dev_id)
> >>    
> >>           marvell_nfc_disable_int(nfc, st & NDCR_ALL_INT);
> >>    
> >> -       if (!(st & (NDSR_RDDREQ | NDSR_WRDREQ | NDSR_WRCMDREQ)))
> >> +       if (st & (NDSR_RDY(0) | NDSR_RDY(1)))
> >>                   complete(&nfc->complete);
> >>    
> >>           return IRQ_HANDLED;  
> > 
> > Yes! That seems to work nicely as a replacement for my patch.
> > 
> > Chris, how is that going on your board?  
> 
> Looks good to me. I've just re-run stress_{1,2,3} on the custom board 
> and DB-88F6820-AMC.

Great! There is still something weird about the complete() though.

Daniel, do you plan to send the above change or do you want me to do
it? I would like to integrate the fix in nand/next before sending the
PR.


Thanks,
Miquèl

  reply	other threads:[~2018-10-03 14:20 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-09-27  7:17 [PATCH v2] mtd: rawnand: marvell: check for RDY bits after enabling the IRQ Daniel Mack
2018-09-27  8:11 ` Miquel Raynal
2018-09-27  8:56   ` Boris Brezillon
2018-09-27 21:55     ` Chris Packham
2018-09-28  6:40       ` Boris Brezillon
2018-09-28  6:56         ` Boris Brezillon
2018-09-28  8:12         ` Miquel Raynal
2018-09-28  7:43       ` Daniel Mack
2018-09-28  8:24         ` Miquel Raynal
2018-09-28  8:29           ` Daniel Mack
2018-09-30 21:10             ` Chris Packham
2018-10-01  5:31               ` Daniel Mack
2018-10-01 19:59                 ` Chris Packham
2018-10-01 20:34                   ` Boris Brezillon
2018-10-01 21:41                     ` Boris Brezillon
2018-10-01 22:01                       ` Chris Packham
2018-10-01 22:13                         ` Boris Brezillon
2018-10-01 22:15                           ` Chris Packham
2018-10-02  9:36                             ` Boris Brezillon
2018-10-02  9:37                               ` Boris Brezillon
2018-10-02  6:46                           ` Miquel Raynal
2018-10-02  7:25                             ` Miquel Raynal
2018-10-02  8:22                               ` Daniel Mack
2018-10-02 20:53                                 ` Chris Packham
2018-10-03  7:33                                   ` Miquel Raynal [this message]
2018-10-03  7:54                                     ` Daniel Mack
2018-10-01 22:44 ` Boris Brezillon
2018-10-02  7:42   ` Daniel Mack

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