From: Greg KH <gregkh@linuxfoundation.org>
To: Sai Praneeth Prakhya <sai.praneeth.prakhya@intel.com>
Cc: stable@vger.kernel.org, Thomas Gleixner <tglx@linutronix.de>,
Tim C Chen <tim.c.chen@intel.com>,
Dave Hansen <dave.hansen@intel.com>,
Ravi Shankar <ravi.v.shankar@intel.com>,
Andi Kleen <ak@linux.intel.com>
Subject: Re: [PATCH] x86/speculation: Support Enhanced IBRS on future CPUs
Date: Wed, 7 Nov 2018 10:25:25 +0100 [thread overview]
Message-ID: <20181107092525.GG31015@kroah.com> (raw)
In-Reply-To: <1541551365-95437-1-git-send-email-sai.praneeth.prakhya@intel.com>
On Tue, Nov 06, 2018 at 04:42:45PM -0800, Sai Praneeth Prakhya wrote:
> From: Sai Praneeth <sai.praneeth.prakhya@intel.com>
>
> [ Upstream commit 706d51681d636a0c4a5ef53395ec3b803e45ed4d ]
>
> Changes from upstream:
> ----------------------
> 1. Use bit 30 of word 7 in cpufeatures for X86_FEATURE_IBRS_ENHANCED as bit 29
> is now used by L1TF.
> 2. Fix some trivial line fuzzing.
>
> Based on kernel version:
> ------------------------
> Linux 4.9.135
This format is very odd, shouldn't it go all below the original ---
line?
Please fix up and resend properly. Also, why 4.9? What is wrong with
4.18.y, 4.14.y, and 4.4.y? Just picking one random kernel in the middle
of the stable releases seems foolish for those users of newer kernels,
right?
thanks,
greg k-h
next prev parent reply other threads:[~2018-11-07 18:55 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-07 0:42 [PATCH] x86/speculation: Support Enhanced IBRS on future CPUs Sai Praneeth Prakhya
2018-11-07 9:25 ` Greg KH [this message]
2018-11-07 18:05 ` Prakhya, Sai Praneeth
-- strict thread matches above, loose matches on Subject: below --
2018-11-07 0:26 Sai Praneeth Prakhya
2018-11-07 9:26 ` Greg KH
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