From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm1-f45.google.com ([209.85.128.45]:52485 "EHLO mail-wm1-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725829AbeKLF0O (ORCPT ); Mon, 12 Nov 2018 00:26:14 -0500 Received: by mail-wm1-f45.google.com with SMTP id r11-v6so6461217wmb.2 for ; Sun, 11 Nov 2018 11:36:49 -0800 (PST) Date: Sun, 11 Nov 2018 19:36:45 +0000 From: Sudip Mukherjee To: Greg Kroah-Hartman Cc: stable@vger.kernel.org, Chris Packham , Stephen Boyd Subject: request for 4.14-stable: 00c5a926af12 ("clk: mvebu: use correct bit for 98DX3236 NAND") Message-ID: <20181111193645.ae72nh3sxisdg2io@debian> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="zd5vkyluvcoepqmj" Content-Disposition: inline Sender: stable-owner@vger.kernel.org List-ID: --zd5vkyluvcoepqmj Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hi Greg, This was not marked for stable but seems it should be in stable. Please apply to your queue of 4.14-stable. -- Regards Sudip --zd5vkyluvcoepqmj Content-Type: text/x-diff; charset=us-ascii Content-Disposition: attachment; filename="0001-clk-mvebu-use-correct-bit-for-98DX3236-NAND.patch" >>From 0b08b65ad657c08a9b8468d64624f6df52a2f863 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Thu, 24 May 2018 17:23:41 +1200 Subject: [PATCH] clk: mvebu: use correct bit for 98DX3236 NAND commit 00c5a926af12a9f0236928dab3dc9faf621406a1 upstream The correct fieldbit value for the NAND PLL reload trigger is 27. Fixes: commit e120c17a70e5 ("clk: mvebu: support for 98DX3236 SoC") Signed-off-by: Chris Packham Signed-off-by: Stephen Boyd Signed-off-by: Sudip Mukherjee --- drivers/clk/mvebu/clk-corediv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/mvebu/clk-corediv.c b/drivers/clk/mvebu/clk-corediv.c index 8491979f4096..68f05c53d40e 100644 --- a/drivers/clk/mvebu/clk-corediv.c +++ b/drivers/clk/mvebu/clk-corediv.c @@ -72,7 +72,7 @@ static const struct clk_corediv_desc mvebu_corediv_desc[] = { }; static const struct clk_corediv_desc mv98dx3236_corediv_desc[] = { - { .mask = 0x0f, .offset = 6, .fieldbit = 26 }, /* NAND clock */ + { .mask = 0x0f, .offset = 6, .fieldbit = 27 }, /* NAND clock */ }; #define to_corediv_clk(p) container_of(p, struct clk_corediv, hw) -- 2.11.0 --zd5vkyluvcoepqmj--