From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.kernel.org ([198.145.29.99]:54746 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727545AbeKSVHE (ORCPT ); Mon, 19 Nov 2018 16:07:04 -0500 Date: Mon, 19 Nov 2018 11:43:48 +0100 From: Greg Kroah-Hartman To: Sudip Mukherjee Cc: stable@vger.kernel.org, Chris Packham , Stephen Boyd Subject: Re: request for 4.14-stable: 00c5a926af12 ("clk: mvebu: use correct bit for 98DX3236 NAND") Message-ID: <20181119104348.GA26120@kroah.com> References: <20181111193645.ae72nh3sxisdg2io@debian> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20181111193645.ae72nh3sxisdg2io@debian> Sender: stable-owner@vger.kernel.org List-ID: On Sun, Nov 11, 2018 at 07:36:45PM +0000, Sudip Mukherjee wrote: > Hi Greg, > > This was not marked for stable but seems it should be in stable. > Please apply to your queue of 4.14-stable. > > -- > Regards > Sudip > >From 0b08b65ad657c08a9b8468d64624f6df52a2f863 Mon Sep 17 00:00:00 2001 > From: Chris Packham > Date: Thu, 24 May 2018 17:23:41 +1200 > Subject: [PATCH] clk: mvebu: use correct bit for 98DX3236 NAND > > commit 00c5a926af12a9f0236928dab3dc9faf621406a1 upstream > > The correct fieldbit value for the NAND PLL reload trigger is 27. > > Fixes: commit e120c17a70e5 ("clk: mvebu: support for 98DX3236 SoC") > Signed-off-by: Chris Packham > Signed-off-by: Stephen Boyd > Signed-off-by: Sudip Mukherjee > --- > drivers/clk/mvebu/clk-corediv.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Now applied, thanks. greg k-h