From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13920C282C3 for ; Thu, 24 Jan 2019 16:34:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D9C55218A2 for ; Thu, 24 Jan 2019 16:34:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1548347648; bh=vFsmyeu7dH9/EfbBoQqHb0ujB0nfWYVh/XmaF0vGOrU=; h=Date:From:To:Cc:Subject:In-Reply-To:References:List-ID:From; b=yH1XCBxBIfK9mYWJiRVf1e6dS1oZJhXY/gVysDfH3FicKT36kGg48Uj7zFrQNRIhs uv+TsaxYR0gpuEPsA5Jm2ZzCYtnf0ynwTTeEMtqd9xcN7lBju5NS/zjvSCmh2Fu6fU W2aP+5HkmtQ02aYXdcIJsKYsSV/kMeI6oYkBG2c4= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727811AbfAXQeI (ORCPT ); Thu, 24 Jan 2019 11:34:08 -0500 Received: from mail.kernel.org ([198.145.29.99]:40158 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727649AbfAXQeI (ORCPT ); Thu, 24 Jan 2019 11:34:08 -0500 Received: from bbrezillon (91-160-177-164.subs.proxad.net [91.160.177.164]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id C25012184C; Thu, 24 Jan 2019 16:34:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1548347647; bh=vFsmyeu7dH9/EfbBoQqHb0ujB0nfWYVh/XmaF0vGOrU=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=KoIq5GDJWmEAy1d0yXQZOZlWf2i2C+rIVLLr4jEopAbGIW94fFKE/084WHHGO0a4q eJzqQv+F6ypDyIF/j8ZucuStHmLNM8B458ukXMOVB2ENGumI+cKWLHcE2sDl4ndV2P EyEm4AppfP3Kvccf4ritBLLbdB+4qWfwEDLS1Yes= Date: Thu, 24 Jan 2019 17:33:57 +0100 From: Boris Brezillon To: Emil Lenngren Cc: Stefan Roese , Richard Weinberger , Miquel Raynal , linux-mtd@lists.infradead.org, Marek Vasut , Brian Norris , David Woodhouse , stable@vger.kernel.org Subject: Re: [PATCH] mtd: spinand: Handle the case where PROGRAM LOAD does not reset the cache Message-ID: <20190124173357.2a4d7f13@bbrezillon> In-Reply-To: References: <20190124142007.11607-1-bbrezillon@kernel.org> <8f80c33f-b236-27e6-3d87-a8362ad41326@denx.de> X-Mailer: Claws Mail 3.16.0 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org On Thu, 24 Jan 2019 17:16:37 +0100 Emil Lenngren wrote: > Hi, > > Den tors 24 jan. 2019 kl 16:28 skrev Stefan Roese : > > > > On 24.01.19 15:20, Boris Brezillon wrote: > > > Looks like PROGRAM LOAD (AKA write cache) does not necessarily reset > > > the cache content to 0xFF (depends on vendor implementation), so we > > > must fill the page cache entirely even if we only want to program the > > > data portion of the page, otherwise we might corrupt the BBM or user > > > data previously programmed in OOB area. > > > > > > Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs") > > > Reported-by: Stefan Roese > > > Cc: > > > Signed-off-by: Boris Brezillon > > > > Works fine (limited testing only yet), so: > > > > Tested-by: Stefan Roese > > Reviewed-by: Stefan Roese > > > > Thanks, > > Stefan > > > > Can this quirk be made vendor specific? We can make it vendor specific, as long as it's an opt-in thing. This way, the default behavior is the safest one, and only when we know a chip does reset the cache content on a PROGRAM LOAD time can we add this flag. > It seems a waste of SPI > transfer cycles to write 0xff to the whole OOB area when we only want > to program the data area if the chip doesn't need this quirk. > For which logic is this needed anyway? According to the GigaDevice > datasheet, if a Program Load is followed by Program Execute, > "uninitialized" bytes will be set to 0xff, which is the flow that is > used by spinand core. Except you're not guaranteed that the controller can fill the page in a single spi_mem_exec_op() call (because of FIFO size limitations), so you might have one PROGRAM LOAD followed by several PROGRAM RANDOM LOAD. I guess most manufacturers reset the cache content at PROGRAM LOAD time, but GigaDevice does not. > > /Emil