From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DBC60C282C0 for ; Fri, 25 Jan 2019 11:09:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id ADCEC218DE for ; Fri, 25 Jan 2019 11:09:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726026AbfAYLJX convert rfc822-to-8bit (ORCPT ); Fri, 25 Jan 2019 06:09:23 -0500 Received: from mail.bootlin.com ([62.4.15.54]:47170 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725909AbfAYLJX (ORCPT ); Fri, 25 Jan 2019 06:09:23 -0500 Received: by mail.bootlin.com (Postfix, from userid 110) id 6B3D320798; Fri, 25 Jan 2019 12:09:20 +0100 (CET) Received: from xps13 (aaubervilliers-681-1-87-206.w90-88.abo.wanadoo.fr [90.88.29.206]) by mail.bootlin.com (Postfix) with ESMTPSA id 21D52206A6; Fri, 25 Jan 2019 12:09:10 +0100 (CET) Date: Fri, 25 Jan 2019 12:09:10 +0100 From: Miquel Raynal To: Boris Brezillon Cc: Emil Lenngren , Stefan Roese , Richard Weinberger , linux-mtd@lists.infradead.org, Marek Vasut , Brian Norris , David Woodhouse , stable@vger.kernel.org Subject: Re: [PATCH] mtd: spinand: Handle the case where PROGRAM LOAD does not reset the cache Message-ID: <20190125120910.59c33a4b@xps13> In-Reply-To: <20190124173357.2a4d7f13@bbrezillon> References: <20190124142007.11607-1-bbrezillon@kernel.org> <8f80c33f-b236-27e6-3d87-a8362ad41326@denx.de> <20190124173357.2a4d7f13@bbrezillon> Organization: Bootlin X-Mailer: Claws Mail 3.17.1 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org Hello, Boris Brezillon wrote on Thu, 24 Jan 2019 17:33:57 +0100: > On Thu, 24 Jan 2019 17:16:37 +0100 > Emil Lenngren wrote: > > > Hi, > > > > Den tors 24 jan. 2019 kl 16:28 skrev Stefan Roese : > > > > > > On 24.01.19 15:20, Boris Brezillon wrote: > > > > Looks like PROGRAM LOAD (AKA write cache) does not necessarily reset > > > > the cache content to 0xFF (depends on vendor implementation), so we > > > > must fill the page cache entirely even if we only want to program the > > > > data portion of the page, otherwise we might corrupt the BBM or user > > > > data previously programmed in OOB area. > > > > > > > > Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs") > > > > Reported-by: Stefan Roese > > > > Cc: > > > > Signed-off-by: Boris Brezillon > > > > > > Works fine (limited testing only yet), so: > > > > > > Tested-by: Stefan Roese > > > Reviewed-by: Stefan Roese > > > > > > Thanks, > > > Stefan > > > > > > > Can this quirk be made vendor specific? > > We can make it vendor specific, as long as it's an opt-in thing. This > way, the default behavior is the safest one, and only when we know a > chip does reset the cache content on a PROGRAM LOAD time can we add this > flag. I am fine with this approach. Thanks, Miquèl