From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17944C282C0 for ; Fri, 25 Jan 2019 16:09:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D7623218D0 for ; Fri, 25 Jan 2019 16:09:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1548432540; bh=4AYDE7Q2U9ps69hXCAJLNw6MCXL2nRTllN7Qw+k29lg=; h=Date:From:To:Cc:Subject:In-Reply-To:References:List-ID:From; b=Ai8Ez4qqz0nBABeGAPUVripXJDILw+MhqRPCvMxxotKoZo6DYjzbkmWrPrRcQdqfn pqFoDnORrdQ1bMoeaZ6RV3k3chJY2r/FqLg7hQcyR4h7pv/WyjiIrxp1iLZZFlqPl6 Lwchbb5M4gA36AsgahOBA6xVR/niidJw+gfD4fTQ= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726265AbfAYQJA (ORCPT ); Fri, 25 Jan 2019 11:09:00 -0500 Received: from mail.kernel.org ([198.145.29.99]:48918 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726108AbfAYQJA (ORCPT ); Fri, 25 Jan 2019 11:09:00 -0500 Received: from bbrezillon (91-160-177-164.subs.proxad.net [91.160.177.164]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 309C4218CD; Fri, 25 Jan 2019 16:08:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1548432539; bh=4AYDE7Q2U9ps69hXCAJLNw6MCXL2nRTllN7Qw+k29lg=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=jMGaP0a3FAsVLj+hLoLaI2P7etfN5qBcdL5ce3O0cElCu79jQiKr99Ay27IsZkjTc 7gNBSJnvtutqwcUdWkVrO4c2+hGWfXe76Jxiu4zxoRJMqg/YSyy3cDJj/7limPuqMd 9itZpbKDTVLBF9VclHUG2OkcFv4PKsHhtz3ljLrA= Date: Fri, 25 Jan 2019 17:08:51 +0100 From: Boris Brezillon To: Miquel Raynal Cc: Emil Lenngren , Stefan Roese , Richard Weinberger , linux-mtd@lists.infradead.org, Marek Vasut , Brian Norris , David Woodhouse , stable@vger.kernel.org Subject: Re: [PATCH] mtd: spinand: Handle the case where PROGRAM LOAD does not reset the cache Message-ID: <20190125170851.3d918da5@bbrezillon> In-Reply-To: <20190125120910.59c33a4b@xps13> References: <20190124142007.11607-1-bbrezillon@kernel.org> <8f80c33f-b236-27e6-3d87-a8362ad41326@denx.de> <20190124173357.2a4d7f13@bbrezillon> <20190125120910.59c33a4b@xps13> X-Mailer: Claws Mail 3.16.0 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org On Fri, 25 Jan 2019 12:09:10 +0100 Miquel Raynal wrote: > Hello, > > Boris Brezillon wrote on Thu, 24 Jan 2019 > 17:33:57 +0100: > > > On Thu, 24 Jan 2019 17:16:37 +0100 > > Emil Lenngren wrote: > > > > > Hi, > > > > > > Den tors 24 jan. 2019 kl 16:28 skrev Stefan Roese : > > > > > > > > On 24.01.19 15:20, Boris Brezillon wrote: > > > > > Looks like PROGRAM LOAD (AKA write cache) does not necessarily reset > > > > > the cache content to 0xFF (depends on vendor implementation), so we > > > > > must fill the page cache entirely even if we only want to program the > > > > > data portion of the page, otherwise we might corrupt the BBM or user > > > > > data previously programmed in OOB area. > > > > > > > > > > Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs") > > > > > Reported-by: Stefan Roese > > > > > Cc: > > > > > Signed-off-by: Boris Brezillon > > > > > > > > Works fine (limited testing only yet), so: > > > > > > > > Tested-by: Stefan Roese > > > > Reviewed-by: Stefan Roese > > > > > > > > Thanks, > > > > Stefan > > > > > > > > > > Can this quirk be made vendor specific? > > > > We can make it vendor specific, as long as it's an opt-in thing. This > > way, the default behavior is the safest one, and only when we know a > > chip does reset the cache content on a PROGRAM LOAD time can we add this > > flag. > > I am fine with this approach. Does that stand for a Reviewed-by/Acked-by? To make it clear, I was saying that we should fix things first (with this fix) and only then optimize things for chips that actually reset the cache when PROGRAM LOAD is executed. I was not planning on sending a new version of this patch, unless you see good reasons to do so.