From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 949C2C169C4 for ; Mon, 11 Feb 2019 15:13:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6487D222A7 for ; Mon, 11 Feb 2019 15:13:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1549897981; bh=jr6RotHTA5TSvTXb30n/QrCaxiV6hIfGvqZ11PaBTIE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=h2s9y9LvVSjDZ3KBqu3iQIe38F4WrwK/jZFfaXyb2n1Vjolc6p7maNRaRqzY2SEyz YX2udJcO3gcOgBb7qeWC2nH29uKSDqOK0qiXlYW7hwDPsw60cqb+RiD+9Pqyml5BYo xwOMdW8uRigxAgQX7fRHBqJgCt7vYxjzscf3ujlY= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2391750AbfBKPNA (ORCPT ); Mon, 11 Feb 2019 10:13:00 -0500 Received: from mail.kernel.org ([198.145.29.99]:59852 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2391117AbfBKPJv (ORCPT ); Mon, 11 Feb 2019 10:09:51 -0500 Received: from localhost (5356596B.cm-6-7b.dynamic.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id BC130222A7; Mon, 11 Feb 2019 15:09:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1549897791; bh=jr6RotHTA5TSvTXb30n/QrCaxiV6hIfGvqZ11PaBTIE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JDYcYKadmMBREKq04uiQx+ILoAfB68qtYvzoK7iV7df+bTLbB7336XnIz11aRLDA8 N072wTsd+wOq3tEN4n4SM3T9phA59ZGVKus0INeDGmoTeunXdCGIo2SXrHfLaI8hcm QP0jHd0HbHJHQq/Jdn441Bfybhxto1Yi5JhFUr/o= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Stefan Roese , Paul Burton , John Crispin , Daniel Schwierzeck , Ralf Baechle , linux-mips@linux-mips.org, Sasha Levin Subject: [PATCH 4.9 086/137] MIPS: ralink: Select CONFIG_CPU_MIPSR2_IRQ_VI on MT7620/8 Date: Mon, 11 Feb 2019 15:19:27 +0100 Message-Id: <20190211141820.009408107@linuxfoundation.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190211141811.964925535@linuxfoundation.org> References: <20190211141811.964925535@linuxfoundation.org> User-Agent: quilt/0.65 X-stable: review X-Patchwork-Hint: ignore MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org 4.9-stable review patch. If anyone has any objections, please let me know. ------------------ [ Upstream commit 0b15394475e3bcaf35ca4bf22fc55d56df67224e ] Testing has shown, that when using mainline U-Boot on MT7688 based boards, the system may hang or crash while mounting the root-fs. The main issue here is that mainline U-Boot configures EBase to a value near the end of system memory. And with CONFIG_CPU_MIPSR2_IRQ_VI disabled, trap_init() will not allocate a new area to place the exception handler. The original value will be used and the handler will be copied to this location, which might already be used by some userspace application. The MT7688 supports VI - its config3 register is 0x00002420, so VInt (Bit 5) is set. But without setting CONFIG_CPU_MIPSR2_IRQ_VI this bit will not be evaluated to result in "cpu_has_vi" being set. This patch now selects CONFIG_CPU_MIPSR2_IRQ_VI on MT7620/8 which results trap_init() to allocate some memory for the exception handler. Please note that this issue was not seen with the Mediatek U-Boot version, as it does not touch EBase (stays at default of 0x8000.0000). This is strictly also not correct as the kernel (_text) resides here. Signed-off-by: Stefan Roese [paul.burton@mips.com: s/beeing/being/] Signed-off-by: Paul Burton Cc: John Crispin Cc: Daniel Schwierzeck Cc: Ralf Baechle Cc: linux-mips@linux-mips.org Signed-off-by: Sasha Levin --- arch/mips/ralink/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig index 813826a456ca..55a5fee781e8 100644 --- a/arch/mips/ralink/Kconfig +++ b/arch/mips/ralink/Kconfig @@ -38,6 +38,7 @@ choice config SOC_MT7620 bool "MT7620/8" + select CPU_MIPSR2_IRQ_VI select HW_HAS_PCI config SOC_MT7621 -- 2.19.1