From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4164FC00319 for ; Tue, 5 Mar 2019 05:06:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1BC3820675 for ; Tue, 5 Mar 2019 05:06:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727114AbfCEFGJ (ORCPT ); Tue, 5 Mar 2019 00:06:09 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:43902 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727036AbfCEFGJ (ORCPT ); Tue, 5 Mar 2019 00:06:09 -0500 X-UUID: a5aae310d0294d73b8e81b522da60fc6-20190305 X-UUID: a5aae310d0294d73b8e81b522da60fc6-20190305 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 2114462826; Tue, 05 Mar 2019 13:05:55 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs02n1.mediatek.inc (172.21.101.77) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 5 Mar 2019 13:05:54 +0800 Received: from mtkslt210.mediatek.inc (10.21.14.14) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 5 Mar 2019 13:05:54 +0800 From: Weiyi Lu To: Nicolas Boichat , Matthias Brugger , Stephen Boyd , Rob Herring CC: James Liao , Fan Chen , , , , , , , Weiyi Lu Subject: [PATCH v5 0/9] Mediatek MT8183 clock support Date: Tue, 5 Mar 2019 13:05:37 +0800 Message-ID: <20190305050546.23431-2-weiyi.lu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190305050546.23431-1-weiyi.lu@mediatek.com> References: <20190305050546.23431-1-weiyi.lu@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org Resend clock patches from v4 based on v5.0-rc1. The whole series now is composed of a fix for PLL tuner (PATCH 1), clock common changes for both MT8183 & MT6765 (PATCH 2-3), clock support of MT8183 (PATCH 4-8) and resend a clock patch long time ago(PTACH 9). changes since v4: - refine for the fix of PLL tuner(PATCH 1). - add configurable pcw_chg_reg for MT8183 and the following IC(PATCH 7). changes sinve v3: - add fix tag. - small change of mtk_clk_mux data structure. - use of_property_for_each_string to iterate dependent subsys clock of power domain. - document critical clocks. - reduce some clock register error log. - few coding style fix. changes sinve v2: - refine for implementation consistency of mtk clk mux. - separate the onoff API into enable/disable API for mtk scpsys. - resend a patch about PLL rate changing. changes since v1: - refine for better code quality. - some minor bug fix of clock part, like incorrect control address and missing clocks. James Liao (1): clk: mediatek: Allow changing PLL rate when it is off Owen Chen (3): clk: mediatek: Disable tuner_en before change PLL rate clk: mediatek: Add new clkmux register API clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_data Weiyi Lu (5): dt-bindings: ARM: Mediatek: Document bindings for MT8183 clk: mediatek: Add dt-bindings for MT8183 clocks clk: mediatek: Add flags support for mtk_gate data clk: mediatek: Add configurable pcw_chg_reg to mtk_pll_data clk: mediatek: Add MT8183 clock support .../arm/mediatek/mediatek,apmixedsys.txt | 1 + .../bindings/arm/mediatek/mediatek,audsys.txt | 1 + .../bindings/arm/mediatek/mediatek,camsys.txt | 22 + .../bindings/arm/mediatek/mediatek,imgsys.txt | 1 + .../arm/mediatek/mediatek,infracfg.txt | 1 + .../bindings/arm/mediatek/mediatek,ipu.txt | 43 + .../bindings/arm/mediatek/mediatek,mcucfg.txt | 1 + .../bindings/arm/mediatek/mediatek,mfgcfg.txt | 1 + .../bindings/arm/mediatek/mediatek,mmsys.txt | 1 + .../arm/mediatek/mediatek,topckgen.txt | 1 + .../arm/mediatek/mediatek,vdecsys.txt | 1 + .../arm/mediatek/mediatek,vencsys.txt | 1 + drivers/clk/mediatek/Kconfig | 75 + drivers/clk/mediatek/Makefile | 15 +- drivers/clk/mediatek/clk-gate.c | 5 +- drivers/clk/mediatek/clk-gate.h | 17 +- drivers/clk/mediatek/clk-mt8183-audio.c | 105 ++ drivers/clk/mediatek/clk-mt8183-cam.c | 63 + drivers/clk/mediatek/clk-mt8183-img.c | 63 + drivers/clk/mediatek/clk-mt8183-ipu0.c | 56 + drivers/clk/mediatek/clk-mt8183-ipu1.c | 56 + drivers/clk/mediatek/clk-mt8183-ipu_adl.c | 54 + drivers/clk/mediatek/clk-mt8183-ipu_conn.c | 123 ++ drivers/clk/mediatek/clk-mt8183-mfgcfg.c | 54 + drivers/clk/mediatek/clk-mt8183-mm.c | 111 ++ drivers/clk/mediatek/clk-mt8183-vdec.c | 67 + drivers/clk/mediatek/clk-mt8183-venc.c | 59 + drivers/clk/mediatek/clk-mt8183.c | 1284 +++++++++++++++++ drivers/clk/mediatek/clk-mtk.c | 3 +- drivers/clk/mediatek/clk-mtk.h | 4 + drivers/clk/mediatek/clk-mux.c | 223 +++ drivers/clk/mediatek/clk-mux.h | 89 ++ drivers/clk/mediatek/clk-pll.c | 87 +- include/dt-bindings/clock/mt8183-clk.h | 422 ++++++ 34 files changed, 3073 insertions(+), 37 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,ipu.txt create mode 100644 drivers/clk/mediatek/clk-mt8183-audio.c create mode 100644 drivers/clk/mediatek/clk-mt8183-cam.c create mode 100644 drivers/clk/mediatek/clk-mt8183-img.c create mode 100644 drivers/clk/mediatek/clk-mt8183-ipu0.c create mode 100644 drivers/clk/mediatek/clk-mt8183-ipu1.c create mode 100644 drivers/clk/mediatek/clk-mt8183-ipu_adl.c create mode 100644 drivers/clk/mediatek/clk-mt8183-ipu_conn.c create mode 100644 drivers/clk/mediatek/clk-mt8183-mfgcfg.c create mode 100644 drivers/clk/mediatek/clk-mt8183-mm.c create mode 100644 drivers/clk/mediatek/clk-mt8183-vdec.c create mode 100644 drivers/clk/mediatek/clk-mt8183-venc.c create mode 100644 drivers/clk/mediatek/clk-mt8183.c create mode 100644 drivers/clk/mediatek/clk-mux.c create mode 100644 drivers/clk/mediatek/clk-mux.h create mode 100644 include/dt-bindings/clock/mt8183-clk.h -- 2.18.0