From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.0 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 324DCC43381 for ; Fri, 22 Mar 2019 12:55:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 00A4221873 for ; Fri, 22 Mar 2019 12:55:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1553259309; bh=IIpXxvVA4xcyGkb092eHJwj132lXLEYErLP8mHgtzUs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=ixS4MNNdJbbXibfNHWQqkwsCDHYqTpNZjb//VpVThoGfy8WSBf3gIblwpQIP6joQL KGDT9Oj0OeymAGUMHZ6Um+Ut7cGfZrN0pynok34iRPzyBqJbKprUrX7vPQLWmMJGvj OFiZ1DYy5jSIZ8pHAVy9ahup8N3wbv+2j0I4rrP8= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732622AbfCVLuV (ORCPT ); Fri, 22 Mar 2019 07:50:21 -0400 Received: from mail.kernel.org ([198.145.29.99]:54152 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732367AbfCVLuV (ORCPT ); Fri, 22 Mar 2019 07:50:21 -0400 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 1B19F20850; Fri, 22 Mar 2019 11:50:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1553255420; bh=IIpXxvVA4xcyGkb092eHJwj132lXLEYErLP8mHgtzUs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=asNYhr/4Yn5ILNnmUg+0P7aVeiwvI4i2lxG/K64+gG0PSHfAMJ6kuz3GT1OrRI6W5 KoKcLOW4sd5OFF4xEWoG2mivzAz3aJ6lkSsWUq12UfIZpS6qS+LG7CNZhvI8rBgeNV J2zm4T2HGtJgh+UpHcfofHOyy/wl0nVu7Gjkfs2E= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Vignesh R , Mark Brown Subject: [PATCH 4.14 086/183] spi: ti-qspi: Fix mmap read when more than one CS in use Date: Fri, 22 Mar 2019 12:15:14 +0100 Message-Id: <20190322111247.968135904@linuxfoundation.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190322111241.819468003@linuxfoundation.org> References: <20190322111241.819468003@linuxfoundation.org> User-Agent: quilt/0.65 X-stable: review X-Patchwork-Hint: ignore MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org 4.14-stable review patch. If anyone has any objections, please let me know. ------------------ From: Vignesh R commit 673c865efbdc5fec3cc525c46d71844d42c60072 upstream. Commit 4dea6c9b0b64 ("spi: spi-ti-qspi: add mmap mode read support") has has got order of parameter wrong when calling regmap_update_bits() to select CS for mmap access. Mask and value arguments are interchanged. Code will work on a system with single slave, but fails when more than one CS is in use. Fix this by correcting the order of parameters when calling regmap_update_bits(). Fixes: 4dea6c9b0b64 ("spi: spi-ti-qspi: add mmap mode read support") Cc: stable@vger.kernel.org Signed-off-by: Vignesh R Signed-off-by: Mark Brown Signed-off-by: Greg Kroah-Hartman --- drivers/spi/spi-ti-qspi.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) --- a/drivers/spi/spi-ti-qspi.c +++ b/drivers/spi/spi-ti-qspi.c @@ -490,8 +490,8 @@ static void ti_qspi_enable_memory_map(st ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG); if (qspi->ctrl_base) { regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg, - MEM_CS_EN(spi->chip_select), - MEM_CS_MASK); + MEM_CS_MASK, + MEM_CS_EN(spi->chip_select)); } qspi->mmap_enabled = true; } @@ -503,7 +503,7 @@ static void ti_qspi_disable_memory_map(s ti_qspi_write(qspi, 0, QSPI_SPI_SWITCH_REG); if (qspi->ctrl_base) regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg, - 0, MEM_CS_MASK); + MEM_CS_MASK, 0); qspi->mmap_enabled = false; }