From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.1 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38D49C10F00 for ; Wed, 27 Mar 2019 18:40:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0904E2070B for ; Wed, 27 Mar 2019 18:40:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1553712008; bh=GXd+FQv0I7gyn1dAW5umAnm2VA0c5bCFeh2R2DDhkws=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=JbM335G+szzgojxSc4p+Uar5WYqtb0dklZa4YNNHDIkXNEOoMGmJPmdV3awWezjGe kWYg8MVDr5xoY6VNIR9YWI3VxmUxjN2dfnDABpZ+glFAm8U2FQ3UljVj21qAaFkzY4 N1PXVxiwtfKsluggu1/i3pW57p7EQ0cCsxoRJ8mQ= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2391051AbfC0SW7 (ORCPT ); Wed, 27 Mar 2019 14:22:59 -0400 Received: from mail.kernel.org ([198.145.29.99]:41180 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2391375AbfC0SW6 (ORCPT ); Wed, 27 Mar 2019 14:22:58 -0400 Received: from sasha-vm.mshome.net (c-73-47-72-35.hsd1.nh.comcast.net [73.47.72.35]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 94A1720449; Wed, 27 Mar 2019 18:22:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1553710977; bh=GXd+FQv0I7gyn1dAW5umAnm2VA0c5bCFeh2R2DDhkws=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=0bkh6MsHOeC/yG3OwQfYq4bJ66+lXMwQ5GIhPJA0QMYaATpA3KrhIhQLVepyZ5CdE 1PveP7oG11ZIFx/KEIATTyZvlgWiDwv9gvJItr9qOdxlnnDsM4tQPsa0TSdhZ69rzJ KGLtb519NB3zWqv9D5ABCGKdUtHYRsgCsUY/zZio= From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Song Hongyan , Jiri Kosina , Sasha Levin , linux-input@vger.kernel.org Subject: [PATCH AUTOSEL 4.9 72/87] HID: intel-ish: ipc: handle PIMR before ish_wakeup also clear PISR busy_clear bit Date: Wed, 27 Mar 2019 14:20:25 -0400 Message-Id: <20190327182040.17444-72-sashal@kernel.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190327182040.17444-1-sashal@kernel.org> References: <20190327182040.17444-1-sashal@kernel.org> MIME-Version: 1.0 X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Song Hongyan [ Upstream commit 2edefc056e4f0e6ec9508dd1aca2c18fa320efef ] Host driver should handle interrupt mask register earlier than wake up ish FW else there will be conditions when FW interrupt comes, host PIMR register still not set ready, so move the interrupt mask setting before ish_wakeup. Clear PISR busy_clear bit in ish_irq_handler. If not clear, there will be conditions host driver received a busy_clear interrupt (before the busy_clear mask bit is ready), it will return IRQ_NONE after check_generated_interrupt, the interrupt will never be cleared, causing the DEVICE not sending following IRQ. Since PISR clear should not be called for the CHV device we do this change. After the change, both ISH2HOST interrupt and busy_clear interrupt will be considered as interrupt from ISH, busy_clear interrupt will return IRQ_HANDLED from IPC_IS_BUSY check. Signed-off-by: Song Hongyan Acked-by: Srinivas Pandruvada Signed-off-by: Jiri Kosina Signed-off-by: Sasha Levin --- drivers/hid/intel-ish-hid/ipc/ipc.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/hid/intel-ish-hid/ipc/ipc.c b/drivers/hid/intel-ish-hid/ipc/ipc.c index 0c9ac4d5d850..41d44536aa15 100644 --- a/drivers/hid/intel-ish-hid/ipc/ipc.c +++ b/drivers/hid/intel-ish-hid/ipc/ipc.c @@ -92,7 +92,10 @@ static bool check_generated_interrupt(struct ishtp_device *dev) IPC_INT_FROM_ISH_TO_HOST_CHV_AB(pisr_val); } else { pisr_val = ish_reg_read(dev, IPC_REG_PISR_BXT); - interrupt_generated = IPC_INT_FROM_ISH_TO_HOST_BXT(pisr_val); + interrupt_generated = !!pisr_val; + /* only busy-clear bit is RW, others are RO */ + if (pisr_val) + ish_reg_write(dev, IPC_REG_PISR_BXT, pisr_val); } return interrupt_generated; @@ -795,11 +798,11 @@ int ish_hw_start(struct ishtp_device *dev) { ish_set_host_rdy(dev); + set_host_ready(dev); + /* After that we can enable ISH DMA operation and wakeup ISHFW */ ish_wakeup(dev); - set_host_ready(dev); - /* wait for FW-initiated reset flow */ if (!dev->recvd_hw_ready) wait_event_interruptible_timeout(dev->wait_hw_ready, -- 2.19.1