From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.0 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7F5D2C04E84 for ; Wed, 15 May 2019 12:06:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 50BF4206BF for ; Wed, 15 May 2019 12:06:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1557922017; bh=PkryYENoIwkRY8gFUuxRQ7rev2NbfZre0BXHHFrzexU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=K4IomG0cRaDKalVK110q6S7yvSiPBKdaFNL9gU63VNnjrPJbW9SqDdHHdMFfkYEdp yujY+90sYOQuuicgANRgaKFOLzoC+CxlKhQS6EcGvprSpA+hZSDhAqpUu/v4Kt3pqT 2TfVfXGigVImzefoHQFXetVc7x8FYpW9HFCaYR7c= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728858AbfEOLJs (ORCPT ); Wed, 15 May 2019 07:09:48 -0400 Received: from mail.kernel.org ([198.145.29.99]:43092 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729104AbfEOLJr (ORCPT ); Wed, 15 May 2019 07:09:47 -0400 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 94A702084E; Wed, 15 May 2019 11:09:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1557918587; bh=PkryYENoIwkRY8gFUuxRQ7rev2NbfZre0BXHHFrzexU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=u/tZZfTfzqAL+oZoeyxcdyh+KizIKAgsEIsxRzjpgud8QM8Hp/KCjBSBAM3MA+/Ym r2uftRxI3WhgR+8n2X1/djmV9aIYVEQnmw/WHlmtdl6bVJI8B4SH/8B01YJXZ1BJZF gHz5D511ULuc/LbIY5FPEYX24CdLweCdbUGw6czE= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Konrad Rzeszutek Wilk , Thomas Gleixner , Kees Cook , kvm@vger.kernel.org, KarimAllah Ahmed , andrew.cooper3@citrix.com, "H. Peter Anvin" , Borislav Petkov , David Woodhouse , Ben Hutchings Subject: [PATCH 4.4 189/266] x86/bugs: Switch the selection of mitigation from CPU vendor to CPU features Date: Wed, 15 May 2019 12:54:56 +0200 Message-Id: <20190515090729.335325918@linuxfoundation.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190515090722.696531131@linuxfoundation.org> References: <20190515090722.696531131@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Konrad Rzeszutek Wilk commit 108fab4b5c8f12064ef86e02cb0459992affb30f upstream. Both AMD and Intel can have SPEC_CTRL_MSR for SSBD. However AMD also has two more other ways of doing it - which are !SPEC_CTRL MSR ways. Signed-off-by: Konrad Rzeszutek Wilk Signed-off-by: Thomas Gleixner Cc: Kees Cook Cc: kvm@vger.kernel.org Cc: KarimAllah Ahmed Cc: andrew.cooper3@citrix.com Cc: "H. Peter Anvin" Cc: Borislav Petkov Cc: David Woodhouse Link: https://lkml.kernel.org/r/20180601145921.9500-4-konrad.wilk@oracle.com Signed-off-by: Ben Hutchings Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/cpu/bugs.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -526,17 +526,12 @@ static enum ssb_mitigation __init __ssb_ * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may * use a completely different MSR and bit dependent on family. */ - switch (boot_cpu_data.x86_vendor) { - case X86_VENDOR_INTEL: - case X86_VENDOR_AMD: - if (!static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) { - x86_amd_ssb_disable(); - break; - } + if (!static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) + x86_amd_ssb_disable(); + else { x86_spec_ctrl_base |= SPEC_CTRL_SSBD; x86_spec_ctrl_mask |= SPEC_CTRL_SSBD; wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); - break; } }