From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.0 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0FCFFC04E53 for ; Wed, 15 May 2019 11:10:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D512F20843 for ; Wed, 15 May 2019 11:09:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1557918599; bh=Jz9Qd95EASPYMKe7kvk/pqXF6X102gSFsEGbQLd1EkI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=p2ymNivX+bmwIhw23eUqLMLNnqwqGWtdTZ783hpPRc15sowvI5xMpekmn5wN1Sf+g J7gB7V9yLPAZcfxBnmRWVHozQ62pBypLYlgyqFikOZlZjrYz6omTkuChppUGTOsI0P CyxzP3PveeJwI+oYhf/MAWkcYQnkPBiLc4h95+5Q= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728789AbfEOLJ5 (ORCPT ); Wed, 15 May 2019 07:09:57 -0400 Received: from mail.kernel.org ([198.145.29.99]:43284 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728865AbfEOLJz (ORCPT ); Wed, 15 May 2019 07:09:55 -0400 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 0E08E20862; Wed, 15 May 2019 11:09:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1557918594; bh=Jz9Qd95EASPYMKe7kvk/pqXF6X102gSFsEGbQLd1EkI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eciQlGLNbqxH8juHyIP3qZa1M3fTHtlBBk0Bh1Y4+EZbnrGyyBWiP/W3OvU14j2iz E4Xdy7hcYbw8P7R5Xche9KZnuZGt2WXrNHKq8+El8MQzWOhvW1kl4zfz84mjeW+WqD uymjxtia7N0W7vc87M8Y+RQXeJ/4gLzf4eMATmB8= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Tom Lendacky , Borislav Petkov , David Woodhouse , Konrad Rzeszutek Wilk , Linus Torvalds , Peter Zijlstra , Thomas Gleixner , Ingo Molnar , Ben Hutchings Subject: [PATCH 4.4 191/266] x86/bugs: Fix the AMD SSBD usage of the SPEC_CTRL MSR Date: Wed, 15 May 2019 12:54:58 +0200 Message-Id: <20190515090729.403842435@linuxfoundation.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190515090722.696531131@linuxfoundation.org> References: <20190515090722.696531131@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Tom Lendacky commit 612bc3b3d4be749f73a513a17d9b3ee1330d3487 upstream. On AMD, the presence of the MSR_SPEC_CTRL feature does not imply that the SSBD mitigation support should use the SPEC_CTRL MSR. Other features could have caused the MSR_SPEC_CTRL feature to be set, while a different SSBD mitigation option is in place. Update the SSBD support to check for the actual SSBD features that will use the SPEC_CTRL MSR. Signed-off-by: Tom Lendacky Cc: Borislav Petkov Cc: David Woodhouse Cc: Konrad Rzeszutek Wilk Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Fixes: 6ac2f49edb1e ("x86/bugs: Add AMD's SPEC_CTRL MSR usage") Link: http://lkml.kernel.org/r/20180702213602.29202.33151.stgit@tlendack-t1.amdoffice.net Signed-off-by: Ingo Molnar Signed-off-by: Ben Hutchings Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/cpu/bugs.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -157,7 +157,8 @@ x86_virt_spec_ctrl(u64 guest_spec_ctrl, guestval |= guest_spec_ctrl & x86_spec_ctrl_mask; /* SSBD controlled in MSR_SPEC_CTRL */ - if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD)) + if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) || + static_cpu_has(X86_FEATURE_AMD_SSBD)) hostval |= ssbd_tif_to_spec_ctrl(ti->flags); if (hostval != guestval) { @@ -526,9 +527,10 @@ static enum ssb_mitigation __init __ssb_ * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may * use a completely different MSR and bit dependent on family. */ - if (!static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) + if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) && + !static_cpu_has(X86_FEATURE_AMD_SSBD)) { x86_amd_ssb_disable(); - else { + } else { x86_spec_ctrl_base |= SPEC_CTRL_SSBD; x86_spec_ctrl_mask |= SPEC_CTRL_SSBD; wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);